| alias.2 | | [ alias Defines an alias for a command, or lists
current alias definitions. ] |
| all_clocks.2 | | [ all_clocks Returns a list of all clocks in the
current design. ] |
| all_cluster_cells.2 | | [ all_cluster_cells
Lists cells contained in the specified
cluster. ] |
| all_clusters.2 | | [ all_clusters Lists clusters associated with the
current_design. ] |
| all_connected.2 | | [ all_connected Returns the objects connected to a net, port, pin, or a net or pin instance. ] |
| all_inputs.2 | | [ all_inputs Returns a list of input ports in the
current design. ] |
| all_outputs.2 | | [ all_outputs Returns a list of output ports in the
current design. ] |
| all_registers.2 | | [ all_registers Returns a list of sequential elements or
pins in the design. ] |
| analyze.2 | | [ analyze Analyzes HDL files and stores the
intermediate format for the HDL
description in the specified library. ] |
| atpg_keep_faults_data.3 | | [ atpg_keep_faults_data ] |
| atpg_test_asynchronous_pins.3 | | [ atpg_test_asynchronous_pins ] |
| atpg_variables.3 | | [ atpg_variables Variables that affect the
create_test_patterns command. ] |
| attributes.3 | | [ attributes Lists the predefined Synopsys
attributes. ] |
| auto_link_disable.3 | | [ auto_link_disable ] |
| auto_wire_load_selection.3 | | [ auto_wire_load_selection ] |
| balance_buffer.2 | | [ balance_buffer Builds a balanced buffer tree on user-
specified nets and drivers. ] |
| balance_registers.2 | | [ balance_registers
Moves the registers of a design to
achieve a minimum cycle time. ] |
| break.2 | | [ break Immediately exits from a loop structure. ] |
| bus_dimension_separator_style.3 | | [ bus_dimension_separator_style ] |
| bus_extraction_style.3 | | [ bus_extraction_style ] |
| bus_inference_descending_sort.3 | | [ bus_inference_descending_sort ] |
| bus_inference_style.3 | | [ bus_inference_style ] |
| bus_minus_style.3 | | [ bus_minus_style ] |
| bus_naming_style.3 | | [ bus_naming_style ] |
| bus_range_separator_style.3 | | [ bus_range_separator_style ] |
| cache_dir_chmod_octal.3 | | [ cache_dir_chmod_octal ] |
| cache_file_chmod_octal.3 | | [ cache_file_chmod_octal ] |
| cache_ls.1 | | [ cache_ls Lists elements in a Synopsys cache. ] |
| cache_read.3 | | [ cache_read ] |
| cache_read_info.3 | | [ cache_read_info ] |
| cache_rm.1 | | [ cache_rm Removes elements from a Synopsys cache. ] |
| cache_write.3 | | [ cache_write ] |
| cache_write_info.3 | | [ cache_write_info ] |
| cd.2 | | [ cd Changes the current directory. ] |
| cell_attributes.3 | | [ cell_attributes
Contains attributes placed on cells. ] |
| change_link.2 | | [ change_link Changes the design to which a cell is
linked. ] |
| change_names.2 | | [ change_names Changes the names of ports, cells, and
nets in a design. ] |
| change_names_update_inst_tree.3 | | [ change_names_update_inst_tree ] |
| characterize.2 | | [ characterize Captures information about the
environment of specific cell instances
and assigns the information as
attributes on the design to which the
cells are linked. ] |
| check_bindings.2 | | [ check_bindings Checks the bindings in a synthetic
library module definition. ] |
| check_design.2 | | [ check_design Checks the current design for
correctness. ] |
| check_implementations.2 | | [ check_implementations
Check the implementations in a synthetic
library module definition. ] |
| check_test.2 | | [ check_test Checks a design against the design rules
of a scan test methodology. ] |
| check_timing.2 | | [ check_timing Warns about possible timing problems in
the current design/fP. ] |
| clock_attributes.3 | | [ clock_attributes
Contains attributes placed on clocks. ] |
| clocks_at.2 | | [ clocks_at
This command is obsolete with v3.1; it
has been replaced by create_clock.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| command_log_file.3 | | [ command_log_file ] |
| company.3 | | [ company ] |
| compare_design.2 | | [ compare_design Compares two designs for functional
equivalence. ] |
| compare_fsm.2 | | [ compare_fsm Compares the sequential behavior of two
finite state machine designs. ] |
| compare_lib.2 | | [ compare_lib Performs a cross-reference check between
a technology library and a symbol
library. ] |
| compatibility_version.3 | | [ compatibility_version ] |
| compile.2 | | [ compile Optimizes a design. ] |
| compile_assume_fully_decoded_three_state_busses.3 | | [ compile_assume_fully_decoded_three_state_busses ] |
| compile_default_critical_range.3 | | [ compile_default_critical_range ] |
| compile_disable_area_opt_during_inplace_opt.3 | | [ compile_disable_area_opt_during_inplace_opt ] |
| compile_disable_hierarchical_inverter_opt.3 | | [ compile_disable_hierarchical_inverter_opt ] |
| compile_dont_touch_annotated_cell_during_inplace_opt.3 | | [ compile_dont_touch_annotated_cell_during_inplace_opt ] |
| compile_fix_multiple_port_nets.3 | | [ compile_fix_multiple_port_nets ] |
| compile_ignore_area_during_inplace_opt.3 | | [ compile_ignore_area_during_inplace_opt ] |
| compile_ignore_footprint_during_inplace_opt.3 | | [ compile_ignore_footprint_during_inplace_opt ] |
| compile_implementation_selection.3 | | [ compile_implementation_selection ] |
| compile_inplace_changed_list_file_name.3 | | [ compile_inplace_changed_list_file_name
NOTE: THIS VARIABLE IS OBSOLETE. Please use the
reoptimize_design_changed_list_file_name variable for
the same functionality. ] |
| compile_instance_name_prefix.3 | | [ compile_instance_name_prefix ] |
| compile_instance_name_suffix.3 | | [ compile_instance_name_suffix ] |
| compile_negative_logic_methodology.3 | | [ compile_negative_logic_methodology ] |
| compile_no_new_cells_at_top_level.3 | | [ compile_no_new_cells_at_top_level ] |
| compile_ok_to_buffer_during_inplace_opt.3 | | [ compile_ok_to_buffer_during_inplace_opt ] |
| compile_preserve_sync_resets.3 | | [ compile_preserve_sync_resets ] |
| compile_update_annotated_delays_during_inplace_opt.3 | | [ compile_update_annotated_delays_during_inplace_opt ] |
| compile_use_low_timing_effort.3 | | [ compile_use_low_timing_effort ] |
| compile_variables.3 | | [ compile_variables
Variables that affect the compile
command. ] |
| connect_net.2 | | [ connect_net Connects a net to pins or ports. ] |
| continue.2 | | [ continue Begins the next loop iteration. ] |
| copy_design.2 | | [ copy_design Copies a design or copies a list of
designs to one file. ] |
| create_bus.2 | | [ create_bus Creates a bus. ] |
| create_cache.2 | | [ create_cache Populates the cache directories with
instances of the requested synthetic
modules. ] |
| create_cell.2 | | [ create_cell Creates cell objects in the
current_design. ] |
| create_clock.2 | | [ create_clock Creates a clock object and defines its
waveform in the current_design. ] |
| create_clock_no_input_delay.3 | | [ create_clock_no_input_delay ] |
| create_design.2 | | [ create_design Creates a design in dc_shell. ] |
| create_net.2 | | [ create_net Creates nets in the current_design. ] |
| create_port.2 | | [ create_port Creates ports in the current_design. ] |
| create_schematic.2 | | [ create_schematic
Generates a schematic for the current
design. ] |
| create_test_clock.2 | | [ create_test_clock
Defines the timing of a clock applied to
a design during manufacturing test. ] |
| create_test_patterns.2 | | [ create_test_patterns
Generates a set of test patterns for a
design. ] |
| create_wire_load.2 | | [ create_wire_load
Creates wire load model(s) for the
current design. ] |
| current_design.2 | | [ current_design Set the working design in dc_shell. ] |
| current_design.3 | | [ current_design ] |
| current_instance.2 | | [ current_instance
Sets the working instance object in
dc_shell. current_instance enables
other commands to be used on a specific
cell in the design hierarchy. ] |
| db2sge.1 | | [ db2sge Transfers symbols and schematics from
Design Analyzer/dc_shell to SGE. ] |
| db2sge_bit_type.3 | | [ db2sge_bit_type ] |
| db2sge_bit_vector_type.3 | | [ db2sge_bit_vector_type ] |
| db2sge_command.3 | | [ db2sge_command ] |
| db2sge_display_instance_names.3 | | [ db2sge_display_instance_names ] |
| db2sge_display_pin_names.3 | | [ db2sge_display_pin_names ] |
| db2sge_display_symbol_names.3 | | [ db2sge_display_symbol_names ] |
| db2sge_one_name.3 | | [ db2sge_one_name ] |
| db2sge_output_directory.3 | | [ db2sge_output_directory ] |
| db2sge_overwrite.3 | | [ db2sge_overwrite ] |
| db2sge_scale.3 | | [ db2sge_scale ] |
| db2sge_script.3 | | [ db2sge_script ] |
| db2sge_target_xp.3 | | [ db2sge_target_xp ] |
| db2sge_tcf_package_file.3 | | [ db2sge_tcf_package_file ] |
| db2sge_unknown_name.3 | | [ db2sge_unknown_name ] |
| db2sge_use_bustaps.3 | | [ db2sge_use_bustaps ] |
| db2sge_use_compound_names.3 | | [ db2sge_use_compound_names ] |
| db2sge_use_lib_section.3 | | [ db2sge_use_lib_section ] |
| db2sge_zero_name.3 | | [ db2sge_zero_name ] |
| dc_shell.1 | | [ dc_shell Runs the Design Analyzer command shell. ] |
| dc_shell_status.3 | | [ dc_shell_status ] |
| default_schematic_options.3 | | [ default_schematic_options ] |
| define_design_lib.2 | | [ define_design_lib
Maps a design library to a UNIX
directory. ] |
| define_name_rules.2 | | [ define_name_rules
Defines a set of name rules for designs. ] |
| derive_clocks.2 | | [ derive_clocks Creates clock objects for network source
pins or ports in the design. ] |
| derive_timing_constraints.2 | | [ derive_timing_constraints
Derives timing requirements and places
that constraint information
on the design. ] |
| design_analyzer.1 | | [ design_analyzer
Runs the Design Analyzer menu interface
in the X Window System. ] |
| design_attributes.3 | | [ design_attributes
Contains attributes placed on designs. ] |
| design_filename_length.3 | | [ design_filename_length ] |
| design_library_file.3 | | [ design_library_file ] |
| designer.3 | | [ designer ] |
| disable_latch_transparency.2 | | [ disable_latch_transparency
This command is replaced by the
set_max_time_borrow command. ] |
| disable_timing.2 | | [ disable_timing
Obsolete. Renamed in v3.1 to
set_disable_timing.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| disconnect_net.2 | | [ disconnect_net Disconnects a net from pins or ports. ] |
| dont_touch.2 | | [ dont_touch
Obsolete. Renamed in v3.1 to
set_dont_touch.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| dont_touch_network.2 | | [ dont_touch_network
Obsolete. Renamed in v3.1 to
set_dont_touch_network.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| dont_use.2 | | [ dont_use
Obsolete. Renamed in v3.1 to
set_dont_use.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| drive_of.2 | | [ drive_of Returns the drive resistance values of
the specified library pin. ] |
| dt_shell.1 | | [ dt_shell Runs the DesignTime command shell. ] |
| duplicate_ports.3 | | [ duplicate_ports ] |
| echo.2 | | [ echo Print out argument values ] |
| echo_include_commands.3 | | [ echo_include_commands ] |
| edif_variables.3 | | [ edif_variables List of global variables that affect the
EDIF format read, read_lib, and write
commands. ] |
| edifin_array_range_extraction_style.3 | | [ edifin_array_range_extraction_style
Obsolete. Replaced in v3.1 by bus_extraction_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| edifin_autoconnect_offPageConnectors.3 | | [ edifin_autoconnect_offPageConnectors ] |
| edifin_autoconnect_ports.3 | | [ edifin_autoconnect_ports ] |
| edifin_dc_script_flag.3 | | [ edifin_dc_script_flag ] |
| edifin_delete_empty_cells.3 | | [ edifin_delete_empty_cells ] |
| edifin_delete_ripper_cells.3 | | [ edifin_delete_ripper_cells ] |
| edifin_ground_net_name.3 | | [ edifin_ground_net_name ] |
| edifin_ground_net_property_name.3 | | [ edifin_ground_net_property_name ] |
| edifin_ground_net_property_value.3 | | [ edifin_ground_net_property_value ] |
| edifin_ground_port_name.3 | | [ edifin_ground_port_name ] |
| edifin_instance_property_name.3 | | [ edifin_instance_property_name ] |
| edifin_lib_in_osc_symbol.3 | | [ edifin_lib_in_osc_symbol ] |
| edifin_lib_in_port_symbol.3 | | [ edifin_lib_in_port_symbol ] |
| edifin_lib_inout_osc_symbol.3 | | [ edifin_lib_inout_osc_symbol ] |
| edifin_lib_inout_port_symbol.3 | | [ edifin_lib_inout_port_symbol ] |
| edifin_lib_logic_0_symbol.3 | | [ edifin_lib_logic_0_symbol ] |
| edifin_lib_logic_1_symbol.3 | | [ edifin_lib_logic_1_symbol ] |
| edifin_lib_mentor_netcon_symbol.3 | | [ edifin_lib_mentor_netcon_symbol ] |
| edifin_lib_out_osc_symbol.3 | | [ edifin_lib_out_osc_symbol ] |
| edifin_lib_out_port_symbol.3 | | [ edifin_lib_out_port_symbol ] |
| edifin_lib_ripper_bits_property.3 | | [ edifin_lib_ripper_bits_property ] |
| edifin_lib_ripper_bus_end.3 | | [ edifin_lib_ripper_bus_end ] |
| edifin_lib_ripper_cell_name.3 | | [ edifin_lib_ripper_cell_name ] |
| edifin_lib_ripper_view_name.3 | | [ edifin_lib_ripper_view_name ] |
| edifin_lib_route_grid.3 | | [ edifin_lib_route_grid ] |
| edifin_lib_templates.3 | | [ edifin_lib_templates ] |
| edifin_portInstance_disabled_property_name.3 | | [ edifin_portInstance_disabled_property_name ] |
| edifin_portInstance_disabled_property_value.3 | | [ edifin_portInstance_disabled_property_value ] |
| edifin_portInstance_property_name.3 | | [ edifin_portInstance_property_name ] |
| edifin_power_net_name.3 | | [ edifin_power_net_name ] |
| edifin_power_net_property_name.3 | | [ edifin_power_net_property_name ] |
| edifin_power_net_property_value.3 | | [ edifin_power_net_property_value ] |
| edifin_power_port_name.3 | | [ edifin_power_port_name ] |
| edifin_use_identifier_in_rename.3 | | [ edifin_use_identifier_in_rename ] |
| edifin_view_identifier_property_name.3 | | [ edifin_view_identifier_property_name ] |
| edifout_array_member_naming_style.3 | | [ edifout_array_member_naming_style
Obsolete. Replaced in v3.1 by bus_naming_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| edifout_array_range_naming_style.3 | | [ edifout_array_range_naming_style
Obsolete. Replaced in v3.1 by bus_naming_style and
bus_range_separator_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| edifout_dc_script_flag.3 | | [ edifout_dc_script_flag ] |
| edifout_design_name.3 | | [ edifout_design_name ] |
| edifout_designs_library_name.3 | | [ edifout_designs_library_name ] |
| edifout_display_instance_names.3 | | [ edifout_display_instance_names ] |
| edifout_display_net_names.3 | | [ edifout_display_net_names ] |
| edifout_external.3 | | [ edifout_external ] |
| edifout_ground_name.3 | | [ edifout_ground_name ] |
| edifout_ground_net_name.3 | | [ edifout_ground_net_name ] |
| edifout_ground_net_property_name.3 | | [ edifout_ground_net_property_name ] |
| edifout_ground_net_property_value.3 | | [ edifout_ground_net_property_value ] |
| edifout_ground_pin_name.3 | | [ edifout_ground_pin_name ] |
| edifout_ground_port_name.3 | | [ edifout_ground_port_name ] |
| edifout_instance_property_name.3 | | [ edifout_instance_property_name ] |
| edifout_instantiate_ports.3 | | [ edifout_instantiate_ports ] |
| edifout_match_vhdl_names.3 | | [ edifout_match_vhdl_names
Became obsolete in v3.1.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| edifout_merge_libraries.3 | | [ edifout_merge_libraries ] |
| edifout_multidimension_arrays.3 | | [ edifout_multidimension_arrays ] |
| edifout_name_oscs_different_from_ports.3 | | [ edifout_name_oscs_different_from_ports ] |
| edifout_name_rippers_same_as_wires.3 | | [ edifout_name_rippers_same_as_wires ] |
| edifout_netlist_only.3 | | [ edifout_netlist_only ] |
| edifout_no_array.3 | | [ edifout_no_array ] |
| edifout_numerical_array_members.3 | | [ edifout_numerical_array_members ] |
| edifout_pin_direction_in_value.3 | | [ edifout_pin_direction_in_value ] |
| edifout_pin_direction_inout_value.3 | | [ edifout_pin_direction_inout_value ] |
| edifout_pin_direction_out_value.3 | | [ edifout_pin_direction_out_value ] |
| edifout_pin_direction_property_name.3 | | [ edifout_pin_direction_property_name ] |
| edifout_pin_name_property_name.3 | | [ edifout_pin_name_property_name ] |
| edifout_portInstance_disabled_property_name.3 | | [ edifout_portInstance_disabled_property_name ] |
| edifout_portInstance_disabled_property_value.3 | | [ edifout_portInstance_disabled_property_value ] |
| edifout_portInstance_property_name.3 | | [ edifout_portInstance_property_name ] |
| edifout_power_and_ground_representation.3 | | [ edifout_power_and_ground_representation ] |
| edifout_power_name.3 | | [ edifout_power_name ] |
| edifout_power_net_name.3 | | [ edifout_power_net_name ] |
| edifout_power_net_property_name.3 | | [ edifout_power_net_property_name ] |
| edifout_power_net_property_value.3 | | [ edifout_power_net_property_value ] |
| edifout_power_pin_name.3 | | [ edifout_power_pin_name ] |
| edifout_power_port_name.3 | | [ edifout_power_port_name ] |
| edifout_skip_port_implementations.3 | | [ edifout_skip_port_implementations ] |
| edifout_target_system.3 | | [ edifout_target_system ] |
| edifout_top_level_symbol.3 | | [ edifout_top_level_symbol ] |
| edifout_translate_origin.3 | | [ edifout_translate_origin ] |
| edifout_unused_property_value.3 | | [ edifout_unused_property_value ] |
| edifout_viewType_GRAPHIC_view_name.3 | | [ edifout_viewType_GRAPHIC_view_name ] |
| edifout_viewType_SCHEMATIC_view_name.3 | | [ edifout_viewType_SCHEMATIC_view_name ] |
| edifout_write_attributes.3 | | [ edifout_write_attributes ] |
| edifout_write_constraints.3 | | [ edifout_write_constraints ] |
| edifout_write_properties_list.3 | | [ edifout_write_properties_list ] |
| elaborate.2 | | [ elaborate Builds a design from the intermediate
format of a verilog module, a VHDL
entity and architecture, or a VHDL
configuration. ] |
| enable_page_mode.3 | | [ enable_page_mode ] |
| equationout_and_sign.3 | | [ equationout_and_sign ] |
| equationout_or_sign.3 | | [ equationout_or_sign ] |
| equationout_postfix_negation.3 | | [ equationout_postfix_negation ] |
| execute.2 | | [ execute Executes command arguments ] |
| exit.2 | | [ exit Exits the dc_shell. ] |
| extract.2 | | [ extract Extracts a state-machine representation
from a netlist or HDL description. ] |
| filter.2 | | [ filter Returns a list of design objects that
satisfy a conditional attribute
expression. ] |
| find.2 | | [ find Finds a design or library object. ] |
| find_converts_name_lists.3 | | [ find_converts_name_lists ] |
| fix_hold.2 | | [ fix_hold
Obsolete. Renamed in v3.1 to
set_fix_hold.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| foreach.2 | | [ foreach Specifies the control structure for
list-traversal loop execution. ] |
| gen_bus_member_naming_style.3 | | [ gen_bus_member_naming_style
Obsolete. Replaced in v3.1 by bus_naming_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| gen_bus_range_naming_style.3 | | [ gen_bus_range_naming_style
Obsolete. Replaced in v3.1 by bus_naming_style and
bus_range_separator_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| gen_bussing_exact_implicit.3 | | [ gen_bussing_exact_implicit ] |
| gen_cell_pin_name_separator.3 | | [ gen_cell_pin_name_separator ] |
| gen_create_netlist_busses.3 | | [ gen_create_netlist_busses ] |
| gen_dont_show_single_bit_busses.3 | | [ gen_dont_show_single_bit_busses ] |
| gen_match_ripper_wire_widths.3 | | [ gen_match_ripper_wire_widths ] |
| gen_max_compound_name_length.3 | | [ gen_max_compound_name_length ] |
| gen_max_ports_on_symbol_side.3 | | [ gen_max_ports_on_symbol_side ] |
| gen_show_created_busses.3 | | [ gen_show_created_busses ] |
| gen_show_created_symbols.3 | | [ gen_show_created_symbols ] |
| gen_single_osc_per_name.3 | | [ gen_single_osc_per_name ] |
| generic_symbol_library.3 | | [ generic_symbol_library ] |
| get_attribute.2 | | [ get_attribute Returns the value of an attribute on a
list of design or library objects. ] |
| get_design_lib_path.2 | | [ get_design_lib_path
Returns the directory to which the
specified library is mapped. ] |
| get_design_parameter.2 | | [ get_design_parameter
Returns the value of a parameter on a
parameterized design object. The
parameter can be a generic in VHDL or a
parameter in Verilog. ] |
| get_license.2 | | [ get_license Obtains a license for a feature. ] |
| get_unix_variable.2 | | [ get_unix_variable
Returns the value of a UNIX environment
variable. ] |
| group.2 | | [ group Creates a new level of hierarchy. ] |
| group_path.2 | | [ group_path Groups a set of paths or endpoints for
cost function calculations. ] |
| group_variable.2 | | [ group_variable Adds a variable to the specified
variable group. This command is
generally used only by the system
administrator. ] |
| hdl_keep_licenses.3 | | [ hdl_keep_licenses ] |
| hdl_preferred_license.3 | | [ hdl_preferred_license ] |
| hdl_variables.3 | | [ hdl_variables Variables that affect reading, writing
and optimizing HDL. ] |
| hdlin_auto_save_templates.3 | | [ hdlin_auto_save_templates ] |
| hdlin_check_no_latch.3 | | [ hdlin_check_no_latch ] |
| hdlin_ff_always_sync_set_reset.3 | | [ hdlin_ff_always_sync_set_reset ] |
| hdlin_files.3 | | [ hdlin_files ] |
| hdlin_latch_always_async_set_reset.3 | | [ hdlin_latch_always_async_set_reset ] |
| hdlin_reg_report_length.3 | | [ hdlin_reg_report_length ] |
| hdlin_replace_synthetic.3 | | [ hdlin_replace_synthetic ] |
| hdlin_report_inferred_modules.3 | | [ hdlin_report_inferred_modules ] |
| hdlin_report_resources.3 | | [ hdlin_report_resources ] |
| hdlin_resource_allocation.3 | | [ hdlin_resource_allocation ] |
| hdlin_resource_implementation.3 | | [ hdlin_resource_implementation ] |
| hdlin_source_to_gates_mode.3 | | [ hdlin_source_to_gates_mode ] |
| hdlin_sync_set_reset.3 | | [ hdlin_sync_set_reset ] |
| hdlin_synch_set_reset.3 | | [ hdlin_synch_set_reset ] |
| help.2 | | [ help Displays reference manual pages for
Synopsys commands. ] |
| highlight_path.2 | | [ highlight_path Highlights timing paths in a schematic. ] |
| history.2 | | [ history Displays previously-executed commands. ] |
| hlo_ignore_priorities.3 | | [ hlo_ignore_priorities ] |
| hlo_minimize_tree_delay.3 | | [ hlo_minimize_tree_delay ] |
| hlo_resource_allocation.3 | | [ hlo_resource_allocation ] |
| hlo_resource_implementation.3 | | [ hlo_resource_implementation ] |
| hlo_share_common_subexpressions.3 | | [ hlo_share_common_subexpressions ] |
| hlo_share_effort.3 | | [ hlo_share_effort ] |
| if.2 | | [ if Conditional execution control structure. ] |
| include.2 | | [ include Executes a script of dc_shell commands. ] |
| insert_jtag.2 | | [ insert_jtag Adds JTAG boundary scan test circuitry
to a design. ] |
| insert_pads.2 | | [ insert_pads Inserts I/O pads in a design. ] |
| insert_test.2 | | [ insert_test Adds test circuitry to a design. ] |
| insert_test_design_naming_style.3 | | [ insert_test_design_naming_style ] |
| insert_test_variables.3 | | [ insert_test_variables
Variables that affect the insert_test
command. ] |
| io_variables.3 | | [ io_variables Variables that affect the read, read_lib, write, and write_lib commands. ] |
| jtag_bsr_cell_port_drive_limit.3 | | [ jtag_bsr_cell_port_drive_limit ] |
| jtag_manufacturer_id.3 | | [ jtag_manufacturer_id ] |
| jtag_part_number.3 | | [ jtag_part_number ] |
| jtag_port_drive_limit.3 | | [ jtag_port_drive_limit ] |
| jtag_test_clock_port_naming_style.3 | | [ jtag_test_clock_port_naming_style ] |
| jtag_test_data_in_port_naming_style.3 | | [ jtag_test_data_in_port_naming_style ] |
| jtag_test_data_out_port_naming_style.3 | | [ jtag_test_data_out_port_naming_style ] |
| jtag_test_mode_select_port_naming_style.3 | | [ jtag_test_mode_select_port_naming_style ] |
| jtag_test_reset_port_naming_style.3 | | [ jtag_test_reset_port_naming_style ] |
| jtag_variables.3 | | [ jtag_variables Variables that affect the insert_jtag
and the set_jtag commands. ] |
| jtag_version_number.3 | | [ jtag_version_number ] |
| library_attributes.3 | | [ library_attributes
Contains attributes placed on libraries. ] |
| library_cell_attributes.3 | | [ library_cell_attributes
Contains attributes placed on library
cells. ] |
| license_users.2 | | [ license_users Lists the current users of the Synopsys
licensed features. ] |
| link.2 | | [ link Resolves design references. ] |
| link_force_case.3 | | [ link_force_case ] |
| link_library.3 | | [ link_library ] |
| links_to_layout_variables.3 | | [ links_to_layout_variables
Variables that affect the
links_to_layout capability. ] |
| list.2 | | [ list Lists information about the commands, variables and licenses currently in the
Design Analyzer or dc_shell. ] |
| list_designs.2 | | [ list_designs List the designs available in dc_shell. ] |
| list_instances.2 | | [ list_instances Lists the instance objects in dc_shell. ] |
| list_libs.2 | | [ list_libs List the available libraries in
dc_shell. ] |
| load_of.2 | | [ load_of Returns the load of a given library pin. ] |
| ls.2 | | [ ls Lists the contents of a directory. ] |
| lsiin_net_name_prefix.3 | | [ lsiin_net_name_prefix ] |
| lsiout_inverter_cell.3 | | [ lsiout_inverter_cell ] |
| lsiout_upcase.3 | | [ lsiout_upcase ] |
| max_area.2 | | [ max_area
Obsolete. Renamed in v3.1 to
set_max_area.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| max_delay.2 | | [ max_delay
Obsolete. Renamed in v3.1 to
set_max_delay.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| max_period.2 | | [ max_period Sets period attribute on clocks in
current_design. ] |
| max_power.2 | | [ max_power
Obsolete. Renamed in v3.1 to
set_max_power.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| mentor_bidirect_value.3 | | [ mentor_bidirect_value ] |
| mentor_do_path.3 | | [ mentor_do_path ] |
| mentor_input_output_property_name.3 | | [ mentor_input_output_property_name ] |
| mentor_input_value.3 | | [ mentor_input_value ] |
| mentor_logic_one_value.3 | | [ mentor_logic_one_value ] |
| mentor_logic_zero_one_property_name.3 | | [ mentor_logic_zero_one_property_name ] |
| mentor_logic_zero_value.3 | | [ mentor_logic_zero_value ] |
| mentor_output_value.3 | | [ mentor_output_value ] |
| mentor_primitive_property_name.3 | | [ mentor_primitive_property_name ] |
| mentor_primitive_property_value.3 | | [ mentor_primitive_property_value ] |
| mentor_reference_property_name.3 | | [ mentor_reference_property_name ] |
| mentor_search_path.3 | | [ mentor_search_path ] |
| mentor_write_symbols.3 | | [ mentor_write_symbols ] |
| min_delay.2 | | [ min_delay
Obsolete. Renamed in v3.1 to
set_min_delay.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| minimize_fsm.2 | | [ minimize_fsm Performs state minimization on a state
table design. ] |
| model.2 | | [ model Creates a model of a design; optionally
adds it to a library. ] |
| net_attributes.3 | | [ net_attributes Contains attributes placed on nets. ] |
| new_model.2 | | |
| parent_cluster.2 | | [ parent_cluster Returns the name of the parent cluster
of the cluster passed. ] |
| pin_attributes.3 | | [ pin_attributes Contains attributes placed on pins. ] |
| pla_read_create_flip_flop.3 | | [ pla_read_create_flip_flop ] |
| plot.2 | | [ plot Plots a design schematic or a design
symbol view in PostScript format. ] |
| plot_box.3 | | [ plot_box ] |
| plot_command.3 | | [ plot_command ] |
| plot_orientation.3 | | [ plot_orientation ] |
| plot_scale_factor.3 | | [ plot_scale_factor ] |
| plot_variables.3 | | [ plot_variables Variables that affect the plot command. ] |
| plotter_maxx.3 | | [ plotter_maxx ] |
| plotter_maxy.3 | | [ plotter_maxy ] |
| plotter_minx.3 | | [ plotter_minx ] |
| plotter_miny.3 | | [ plotter_miny ] |
| port_attributes.3 | | [ port_attributes
Contains attributes placed on ports. ] |
| port_complement_naming_style.3 | | [ port_complement_naming_style ] |
| prefer.2 | | [ prefer
Obsolete. Renamed in v3.1 to
set_prefer.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1 ] |
| probe_point.2 | | [ probe_point This command is replaced by the
report_timing -to command. ] |
| pwd.2 | | [ pwd Displays the pathname of the present
working directory (pwd), also called the
current directory. ] |
| quit.2 | | [ quit Exits dc_shell ] |
| read.2 | | [ read Reads designs into dc_shell. ] |
| read_array_minus_style.3 | | [ read_array_minus_style
Obsolete. Replaced in v3.1 by bus_minus_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| read_array_naming_style.3 | | [ read_array_naming_style
Obsolete. Replaced in v3.1 by bus_naming_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| read_array_separator_style.3 | | [ read_array_separator_style
Obsolete. Replaced in v3.1 by
bus_dimension_separator_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| read_cell_transition.3 | | [ read_cell_transition ] |
| read_clusters.2 | | [ read_clusters Annotates a design with physical cluster
hierarchy data. ] |
| read_inferred_bus_naming_style.3 | | [ read_inferred_bus_naming_style
Obsolete. Replaced in v3.1 by
bus_inference_descending_sort and bus_inference_style.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 4-1 ] |
| read_init_protocol.2 | | [ read_init_protocol
Reads an initialization protocol file. ] |
| read_lib.2 | | [ read_lib Reads a technology or symbol library
into dc_shell. ] |
| read_net_transition.3 | | [ read_net_transition ] |
| read_only_attributes.3 | | [ read_only_attributes
Lists informational attributes placed. ] |
| read_test_protocol.2 | | [ read_test_protocol
Reads a test protocol file. ] |
| read_timing.2 | | [ read_timing Reads leaf-cell and net timing
information from a disk file and
annotates the current_design. ] |
| reduce_fsm.2 | | [ reduce_fsm Reduces the logic for each state
transition in a state table design. ] |
| reference_attributes.3 | | [ reference_attributes
Contains attributes placed on
references. ] |
| remove_annotated_delay.2 | | [ remove_annotated_delay
Removes the annotated delay between two
pins. ] |
| remove_attribute.2 | | [ remove_attribute
Removes an attribute from a design or
library object. ] |
| remove_bus.2 | | [ remove_bus Removes a bus object. ] |
| remove_cache.2 | | [ remove_cache Selectively remove elements from the
synthetic library cache directories. ] |
| remove_cell.2 | | [ remove_cell Removes cells from the current_design. ] |
| remove_clock.2 | | [ remove_clock Removes clocks from the current_design. ] |
| remove_clusters.2 | | [ remove_clusters
Removes the physical cluster hierarchy
associated with a design. ] |
| remove_constraint.2 | | [ remove_constraint
Removes all constraint attributes, clocks, and path delay information from
the current_design. ] |
| remove_design.2 | | [ remove_design Removes a list of designs or libraries
from dc_shell memory. ] |
| remove_highlighting.2 | | [ remove_highlighting
Removes highlighting from schematics of
the current_instance or the
current_design. ] |
| remove_input_delay.2 | | [ remove_input_delay
Removes input delay on pins or input
ports. ] |
| remove_license.2 | | [ remove_license Removes a licensed feature. ] |
| remove_net.2 | | [ remove_net Removes nets from the current_design. ] |
| remove_output_delay.2 | | [ remove_output_delay
Removes output delay on pins or output
ports. ] |
| remove_package.2 | | [ remove_package Deletes VHDL packages from dc_shell. ] |
| remove_pads.2 | | [ remove_pads Removes I/O pads from a design. ] |
| remove_port.2 | | [ remove_port Removes ports from the current_design. ] |
| remove_variable.2 | | [ remove_variable
Removes a variable from dc_shell. ] |
| rename_design.2 | | [ rename_design Renames a design in dc_shell or moves a
list of designs to a file. ] |
| reoptimize_design.2 | | [ reoptimize_design
Incrementally optimizes design utilizing
layout/floorplanning information. ] |
| reoptimize_design_changed_list_file_name.3 | | [ reoptimize_design_changed_list_file_name ] |
| replace_fpga.2 | | [ replace_fpga Replaces field programmable cells in the
current_design with gates in the
target_library. ] |
| replace_synthetic.2 | | [ replace_synthetic
Implements all synthetic library parts
of a design using generic logic. ] |
| report.2 | | [ report This command is replaced by the
individual report commands described
below. ] |
| report_annotated_delay.2 | | [ report_annotated_delay
Displays all annotated information on
cells and nets of the current_design. ] |
| report_area.2 | | [ report_area Displays area information and statistics
for the design of the current_instance, if set; or for the current_design
otherwise. ] |
| report_attribute.2 | | [ report_attribute
Displays attributes and their values
associated with an object. An object
can be a cell, net, pin, port, instance, or a design. ] |
| report_bus.2 | | [ report_bus Lists the bussed ports and nets in the
current_instance, if set; or in the
current_design otherwise. ] |
| report_cache.2 | | [ report_cache Report on the contents of synthetic
library caches. ] |
| report_cell.2 | | [ report_cell Displays information about cells in the
current_instance, if set; or in the
current_design otherwise. ] |
| report_clock.2 | | [ report_clock Displays clock-related information on
the current design. ] |
| report_clusters.2 | | [ report_clusters
Reports on the physical cluster
hierarchy associated with the current
design. ] |
| report_compile_options.2 | | [ report_compile_options
Displays information about the compile
options for the design of the
current_instance, if set; or for the
current_design otherwise. ] |
| report_constraint.2 | | [ report_constraint
Displays constraint-related information
about a design. ] |
| report_delay_calculation.2 | | [ report_delay_calculation
Displays the actual calculation of a
cell or net timing arc delay value ] |
| report_design.2 | | [ report_design Displays attributes on the current
design. ] |
| report_design_lib.2 | | [ report_design_lib
Lists the design units contained in the
specified libraries. ] |
| report_fpga.2 | | [ report_fpga Reports information about resource usage
for supported FPGA architecture. ] |
| report_fsm.2 | | [ report_fsm Displays state-machine attributes and
information for the design of the
current_instance, if set; or for the
current_design otherwise. ] |
| report_hierarchy.2 | | [ report_hierarchy
Displays the reference hierarchy of the
current_instance, if set; or of the
current_design otherwise. ] |
| report_internal_loads.2 | | [ report_internal_loads
Displays internal loads on the nets in
the current design. ] |
| report_lib.2 | | [ report_lib Displays information about technology or
symbol libraries. ] |
| report_name_rules.2 | | [ report_name_rules
Reports the values of name rules. ] |
| report_names.2 | | [ report_names Reports potential name changes in a
design. ] |
| report_net.2 | | [ report_net Displays net information for the design
of the current_instance, if set; or for
the current_design otherwise. ] |
| report_path_group.2 | | [ report_path_group
Reports information about path groups in
the current_design. ] |
| report_port.2 | | [ report_port Displays information about ports for the
design of the current_instance, if set;
or for the current_design otherwise. ] |
| report_power.2 | | [ report_power Displays information about the static
power of the current design. ECL
Compiler only. ] |
| report_reference.2 | | [ report_reference
Displays information about references in
the current_instance, if set; or in the
current_design otherwise. ] |
| report_resources.2 | | [ report_resources
Lists the resources used in the design
of the current_instance, if set; or in
the current_design otherwise. ] |
| report_routability.2 | | [ report_routability
Displays information about the
routability of the current design. ] |
| report_synlib.2 | | [ report_synlib Displays information about synthetic
libraries. ] |
| report_test.2 | | [ report_test Displays test-related information about
the current_design. ] |
| report_timing.2 | | [ report_timing Displays timing information about a
design. ] |
| report_timing_requirements.2 | | [ report_timing_requirements
Reports timing path requirements (user
attributes) and related information. ] |
| report_transitive_fanin.2 | | [ report_transitive_fanin
Reports logic in the transitive fanin of
specified sinks. ] |
| report_transitive_fanout.2 | | [ report_transitive_fanout
Reports logic in the transitive fanout
of specified sources. ] |
| report_wire_load.2 | | [ report_wire_load
Displays the characteristics of the wire
load models set on a design or in a
library. ] |
| report_xref.2 | | [ report_xref Generates a cross-reference between
schematic objects and sheets on which
they occur. ] |
| reset_design.2 | | [ reset_design Removes from the current_design all
user-specified objects and attributes, except those defined using
set_attribute. ] |
| reset_path.2 | | [ reset_path Resets specified paths to single cycle
timing. ] |
| schematic_variables.3 | | [ schematic_variables
Variables that affect create_schematic. ] |
| sdfin_fall_cell_delay_type.3 | | [ sdfin_fall_cell_delay_type ] |
| sdfin_fall_net_delay_type.3 | | [ sdfin_fall_net_delay_type ] |
| sdfin_min_fall_cell_delay.3 | | [ sdfin_min_fall_cell_delay ] |
| sdfin_min_fall_net_delay.3 | | [ sdfin_min_fall_net_delay ] |
| sdfin_min_rise_cell_delay.3 | | [ sdfin_min_rise_cell_delay ] |
| sdfin_min_rise_net_delay.3 | | [ sdfin_min_rise_net_delay ] |
| sdfin_rise_cell_delay_type.3 | | [ sdfin_rise_cell_delay_type ] |
| sdfin_rise_net_delay_type.3 | | [ sdfin_rise_net_delay_type ] |
| sdfin_top_instance_name.3 | | [ sdfin_top_instance_name ] |
| sdfout_min_fall_cell_delay.3 | | [ sdfout_min_fall_cell_delay ] |
| sdfout_min_fall_net_delay.3 | | [ sdfout_min_fall_net_delay ] |
| sdfout_min_rise_cell_delay.3 | | [ sdfout_min_rise_cell_delay ] |
| sdfout_min_rise_net_delay.3 | | [ sdfout_min_rise_net_delay ] |
| sdfout_time_scale.3 | | [ sdfout_time_scale ] |
| sdfout_top_instance_name.3 | | [ sdfout_top_instance_name ] |
| sdfout_write_to_output.3 | | [ sdfout_write_to_output ] |
| search_path.3 | | [ search_path ] |
| set_annotated_delay.2 | | [ set_annotated_delay
Sets the net or cell delay value between
two pins. ] |
| set_arrival.2 | | [ set_arrival Sets the arrival time on input pins or
input ports. ] |
| set_attribute.2 | | [ set_attribute Sets the value of an attribute on a
design or library object. ] |
| set_balance_registers.2 | | [ set_balance_registers
Determines whether a design is retimed
during compile. ] |
| set_boundary_optimization.2 | | [ set_boundary_optimization
Allows for cell, design, or reference
optimization across hierarchical
boundaries. ] |
| set_clock.2 | | [ set_clock This command is replaced by the
set_clock_skew and set_multicycle_path
commands. ] |
| set_clock_skew.2 | | [ set_clock_skew Sets clock skew attributes on clock
objects or flip-flop clock pins. ] |
| set_connect_delay.2 | | [ set_connect_delay
This command is replaced by the
set_annotated_delay command with -net
option. ] |
| set_connection_class.2 | | [ set_connection_class
Sets the connection class value on
ports. ] |
| set_default_flip_flop_type.2 | | [ set_default_flip_flop_type
This command is replaced by the
set_register_type command. ] |
| set_design_license.2 | | [ set_design_license
Adds license information to a design.
set_design_license can be used to
require a license before a design can be
read in. ] |
| set_disable_timing.2 | | [ set_disable_timing
Disables timing arcs in a circuit. ] |
| set_dont_touch.2 | | [ set_dont_touch Sets the dont_touch attribute on cells, nets, or references. ] |
| set_dont_touch_network.2 | | [ set_dont_touch_network
Sets the dont_touch_network attribute on
clocks, pins or ports in a design. ] |
| set_dont_use.2 | | [ set_dont_use Sets the dont_use attribute on library
objects. ] |
| set_drive.2 | | [ set_drive Sets the drive resistance of input or
inout ports. ] |
| set_driving_cell.2 | | [ set_driving_cell
Sets attributes on input or inout ports
specifying that a library cell or pin
will drive the ports. The transition
delay of the ports is determined by the
drive capability of the library cell. ] |
| set_equal.2 | | [ set_equal Defines two input ports as logically
equivalent. ] |
| set_false_path.2 | | [ set_false_path Marks paths between specified points
false. ] |
| set_fanout_load.2 | | [ set_fanout_load
Sets the fanout load value on an output
port of a design. ] |
| set_fix_hold.2 | | [ set_fix_hold Sets a fix_hold attribute on clocks in
the current_design. ] |
| set_flatten.2 | | [ set_flatten Enables or disables the flattening
optimization step during compile. ] |
| set_flip_flop_type.2 | | [ set_flip_flop_type
This command is replaced by the
set_register_type command. ] |
| set_fsm_encoding.2 | | [ set_fsm_encoding
Specifies the bit encodings for states
in the current design. ] |
| set_fsm_encoding_style.2 | | [ set_fsm_encoding_style
Defines the encoding style for assigning
unencoded states. ] |
| set_fsm_minimize.2 | | [ set_fsm_minimize
Determines if state-minimization is to
be performed on the state machine design
during compile. ] |
| set_fsm_order.2 | | [ set_fsm_order Sets the ordering of states in a state
machine design. ] |
| set_fsm_preserve_state.2 | | [ set_fsm_preserve_state
Specifies states to be preserved during
state minimization. ] |
| set_fsm_state_vector.2 | | [ set_fsm_state_vector
Specifies the instance names for flip-
flops used to implement the state
vector. ] |
| set_impl_priority.2 | | [ set_impl_priority
Sets the formula attribute of the
priority parameter and/or the set_id
attribute for implementations in
synthetic libraries. ] |
| set_implementation.2 | | [ set_implementation
Specifies the implementation to use for
synthetic library cell instances in a
design. ] |
| set_input_delay.2 | | [ set_input_delay
Sets input delay on pins or input ports
relative to a clock signal. ] |
| set_jtag_bsr_control_impl.2 | | [ set_jtag_bsr_control_impl
Specifies the JTAG Boundary Scan
Register (BSR) cell implementation used
to synthesize some or all BSR control
cells. ] |
| set_jtag_bsr_input_impl.2 | | [ set_jtag_bsr_input_impl
Specifies the JTAG Boundary Scan
Register (BSR) cell implementation used
to synthesize some or all BSR input
cells. ] |
| set_jtag_bsr_output_impl.2 | | [ set_jtag_bsr_output_impl
Specifies the JTAG Boundary Scan
Register (BSR) cell implementation used
to synthesize some or all BSR output
cells. ] |
| set_jtag_implementation.2 | | [ set_jtag_implementation
Specifies the implementation of a JTAG
component used during JTAG synthesis. ] |
| set_jtag_instruction.2 | | [ set_jtag_instruction
Specifies a JTAG boundary scan
instruction that is recognized, decoded
and acted upon by the synthesized JTAG
test circuitry. ] |
| set_jtag_manufacturer_id.2 | | [ set_jtag_manufacturer_id
Sets the manufacturer identification
number of a set of designs. ] |
| set_jtag_part_number.2 | | [ set_jtag_part_number
Specifies the part number of a list of
designs. ] |
| set_jtag_port.2 | | [ set_jtag_port Specifies the ports to be excluded from
or included in the JTAG Boundary Scan
Register (BSR). ] |
| set_jtag_port_mode.2 | | [ set_jtag_port_mode
Specifies the JTAG operational mode of
ports in the Boundary Scan Register
(BSR). ] |
| set_jtag_port_routing_order.2 | | [ set_jtag_port_routing_order
Specifies the order in which JTAG
boundary scan cells associated with I/O
ports are connected in the Boundary Scan
Register. ] |
| set_jtag_port_type.2 | | [ set_jtag_port_type
Specifies the signal data type of ports
in the Boundary Scan Register (BSR). ] |
| set_jtag_version_number.2 | | [ set_jtag_version_number
Specifies the version number of a set of
designs. ] |
| set_layer.2 | | [ set_layer Defines features of a schematic layer. ] |
| set_load.2 | | [ set_load Sets the load value on ports and nets. ] |
| set_local_link_library.2 | | [ set_local_link_library
Adds a local link library to a design. ] |
| set_logic_one.2 | | [ set_logic_one Specifies that an input port is driven
by logic 1. The set_logic_zero command
is used the same way as this command.
Details for both commands are provided
below. ] |
| set_logic_zero.2 | | [ set_logic_zero Specifies that an input port is driven
by logic 0. The set_logic_one command
is used the same way as this command.
Details for both commands are provided
below. ] |
| set_map_only.2 | | [ set_map_only Sets the map_only attribute on specified
objects so that they can be excluded
from logic-level optimization during
compile. ] |
| set_max_area.2 | | [ set_max_area Sets the max_area attribute for a
design. ] |
| set_max_capacitance.2 | | [ set_max_capacitance
Sets a maximum capacitance value on
ports or designs. ] |
| set_max_delay.2 | | [ set_max_delay Specifies a maximum delay target for
paths in the current_design. ] |
| set_max_fanout.2 | | [ set_max_fanout Sets the maximum fanout for input ports
or designs. ] |
| set_max_power.2 | | [ set_max_power Sets the target power for an ECL design. ] |
| set_max_time_borrow.2 | | [ set_max_time_borrow
Constrains the amount of time borrowing
possible for a level-sensitive latch. ] |
| set_max_transition.2 | | [ set_max_transition
Sets a maximum transition time on ports
or designs. ] |
| set_min_delay.2 | | [ set_min_delay Specifies a minimum delay target for
paths in the current_design. ] |
| set_min_fault_coverage.2 | | [ set_min_fault_coverage
Specifies the minimum acceptable fault
coverage for the design. ] |
| set_min_porosity.2 | | [ set_min_porosity
Sets the minimum porosity for designs. ] |
| set_minimize_tree_delay.2 | | [ set_minimize_tree_delay
Determines whether an arithmetic
expression tree will be restructured to
minimize delay during compile. By
default, all expression trees are
candidates for tree height minimization
if timing constraints are specified. ] |
| set_model_drive.2 | | [ set_model_drive
Sets the model drive value of input or
inout ports. ] |
| set_model_load.2 | | [ set_model_load Sets the model load value on ports. ] |
| set_model_map_effort.2 | | [ set_model_map_effort
Sets the map effort on the current
design during modelling. ] |
| set_model_scale.2 | | [ set_model_scale
Sets the model scale value on the
current_design. ] |
| set_multicycle_path.2 | | [ set_multicycle_path
Modifies the single-cycle timing
relationship of a constrained path. ] |
| set_operating_conditions.2 | | [ set_operating_conditions
Defines the operating conditions for the
current design. ] |
| set_opposite.2 | | [ set_opposite Defines two input ports as logically
opposite. ] |
| set_output_delay.2 | | [ set_output_delay
Sets output delay on pins or output
ports relative to a clock signal. ] |
| set_pad_type.2 | | [ set_pad_type Indicates the type of I/O pads needed on
given ports. ] |
| set_port_is_pad.2 | | [ set_port_is_pad
Marks a port as requiring an I/O pad
attached to it. ] |
| set_prefer.2 | | [ set_prefer Sets the preferred attribute on
specified library gates. ] |
| set_register_type.2 | | [ set_register_type
Specifies latch or flip-flop type
information for designs or cell
instances. ] |
| set_resistance.2 | | [ set_resistance Sets the resistance value on nets. ] |
| set_resource_allocation.2 | | [ set_resource_allocation
Specifies the type of resource
allocation on a design. ] |
| set_resource_implementation.2 | | [ set_resource_implementation
Specifies the type of resource
implementation for the design. ] |
| set_scan.2 | | [ set_scan Determines if sequential cells are
replaced by scan cells and considered
part of the scan path. ] |
| set_scan_chain.2 | | [ set_scan_chain Determines the scan chain in which the
specified cells are connected. ] |
| set_scan_style.2 | | [ set_scan_style Specifies the scan-test implementation
style for a design. ] |
| set_share_cse.2 | | [ set_share_cse Determines whether common subexpressions
are shared during compile. By default, all common subexpressions are shared
unless otherwise specified. ] |
| set_signal_type.2 | | [ set_signal_type
Sets the signal-type on a list of pins
or ports. ] |
| set_structure.2 | | [ set_structure Determines if a design is structured
during optimization. ] |
| set_test_assume.2 | | [ set_test_assume
Specifies a fixed, assumed value at
black-box cell output pins during test
design rule checking and pattern
generation. ] |
| set_test_dont_fault.2 | | [ set_test_dont_fault
Sets the test_dont_fault attribute on
cells, pins, or ports. ] |
| set_test_hold.2 | | [ set_test_hold Specifies a fixed, held value at input
ports during testing. ] |
| set_test_initial.2 | | [ set_test_initial
Specifies a logic value to be initially
assumed at cell output pins during test
design rule checking. ] |
| set_test_isolate.2 | | [ set_test_isolate
Specifies that cells, pins or ports are
logically isolated and considered
untestable during test design rule
checking. ] |
| set_test_methodology.2 | | [ set_test_methodology
Specifies the test implementation
methodology for a design. ] |
| set_test_require.2 | | [ set_test_require
Specifies that generated test vectors
maintain a specified value at a pin. ] |
| set_test_routing_order.2 | | [ set_test_routing_order
Specifies a preferred order in which
scan cells in the design are serially
connected. ] |
| set_timing_ranges.2 | | [ set_timing_ranges
Sets timing ranges for the current
design. ] |
| set_unconnected.2 | | [ set_unconnected
Specifies an unused output port. ] |
| set_ungroup.2 | | [ set_ungroup Instructs compile to ungroup the
specified designs, cells, or references. ] |
| set_unix_variable.2 | | [ set_unix_variable
Sets the value of a UNIX environment
variable. ] |
| set_wire_load.2 | | [ set_wire_load Sets the wire loading model for the
current design or for the specified
cluster or ports. ] |
| set_wired_logic_disable.2 | | [ set_wired_logic_disable
Determines if wired logic may be created
when optimizing an ECL design. ] |
| sh.2 | | [ sh Sends a command to the UNIX operating
system. ] |
| simulation_library.3 | | [ simulation_library ] |
| single_group_per_sheet.3 | | [ single_group_per_sheet ] |
| sort_outputs.3 | | [ sort_outputs ] |
| suffix_variables.3 | | [ suffix_variables
Variables that define the standard
suffixes for files used by the design
and test compilers. ] |
| suppress_errors.3 | | [ suppress_errors ] |
| symbol_library.3 | | [ symbol_library ] |
| synlib_disable_limited_licenses.3 | | [ synlib_disable_limited_licenses ] |
| synlib_dont_get_license.3 | | [ synlib_dont_get_license ] |
| synlib_evaluation_mode.3 | | [ synlib_evaluation_mode ] |
| synlib_model_map_effort.3 | | [ synlib_model_map_effort ] |
| synlib_optimize_non_cache_elements.3 | | [ synlib_optimize_non_cache_elements ] |
| synlib_variables.3 | | [ synlib_variables
Variables that affect the cache_ls
command. ] |
| synopsys_users.1 | | [ synopsys_users Lists the current users of the Synopsys
licensed features. ] |
| synthetic_library.3 | | [ synthetic_library ] |
| system_variables.3 | | [ system_variables
Variables that affect Synopsys commands. ] |
| target_library.3 | | [ target_library ] |
| target_system.3 | | [ target_system ] |
| tdlout_upcase.3 | | [ tdlout_upcase ] |
| template_naming_style.3 | | [ template_naming_style ] |
| template_parameter_style.3 | | [ template_parameter_style ] |
| template_separator_style.3 | | [ template_separator_style ] |
| test_clock_port_naming_style.3 | | [ test_clock_port_naming_style ] |
| test_default_bidir_delay.3 | | [ test_default_bidir_delay ] |
| test_default_delay.3 | | [ test_default_delay ] |
| test_default_min_fault_coverage.3 | | [ test_default_min_fault_coverage ] |
| test_default_period.3 | | [ test_default_period ] |
| test_default_strobe.3 | | [ test_default_strobe ] |
| test_default_strobe_width.3 | | [ test_default_strobe_width ] |
| test_scan_clock_a_port_naming_style.3 | | [ test_scan_clock_a_port_naming_style ] |
| test_scan_clock_b_port_naming_style.3 | | [ test_scan_clock_b_port_naming_style ] |
| test_scan_clock_port_naming_style.3 | | [ test_scan_clock_port_naming_style ] |
| test_scan_enable_inverted_port_naming_style.3 | | [ test_scan_enable_inverted_port_naming_style ] |
| test_scan_enable_port_naming_style.3 | | [ test_scan_enable_port_naming_style ] |
| test_scan_in_port_naming_style.3 | | [ test_scan_in_port_naming_style ] |
| test_scan_out_port_naming_style.3 | | [ test_scan_out_port_naming_style ] |
| test_variables.3 | | [ test_variables Variables that affect the
set_test_methodology, read_test_protocol, check_test, create_test_patterns, insert_test, and
write_test commands. ] |
| text_change_select_region_mode.3 | | [ text_change_select_region_mode ] |
| text_editor_command.3 | | [ text_editor_command ] |
| text_print_command.3 | | [ text_print_command ] |
| timing_variables.3 | | [ timing_variables
Variables that affect timing. ] |
| trace_nets.2 | | [ trace_nets Enables global net tracing during
check_test on the specified nets in the
current_design. ] |
| translate.2 | | [ translate Translates a design from one technology
to another. ] |
| unalias.2 | | [ unalias Removes alias definitions. ] |
| ungroup.2 | | [ ungroup Removes a level of hierarchy. ] |
| uniquify.2 | | [ uniquify Generates designs with unique names for
all cells and references in the current
design hierarchy. ] |
| uniquify_naming_style.3 | | [ uniquify_naming_style ] |
| untrace_nets.2 | | [ untrace_nets Disables global net tracing during
check_test on all specified nets that
had net tracing previously enabled by
trace_nets. ] |
| update_clusters.2 | | [ update_clusters
Updates the clusters associated with the
current_design to reflect the changes
made to a sub-design. ] |
| update_lib.2 | | [ update_lib Updates existing technology, synthetic, or symbol libraries. ] |
| update_script.2 | | [ update_script Modifies an old script to use current
dc_shell commands. ] |
| update_timing.2 | | [ update_timing Updates timing information on the
current design. ] |
| use_port_name_for_oscs.3 | | [ use_port_name_for_oscs ] |
| verbose_messages.3 | | [ verbose_messages ] |
| verilogout_equation.3 | | [ verilogout_equation ] |
| verilogout_higher_designs_first.3 | | [ verilogout_higher_designs_first ] |
| verilogout_ignore_case.3 | | [ verilogout_ignore_case ] |
| verilogout_no_tri.3 | | [ verilogout_no_tri ] |
| verilogout_single_bit.3 | | [ verilogout_single_bit ] |
| vhdlio_variables.3 | | [ vhdlio_variables
Variables that affect the write and
write_lib commands for writing VHDL
format and generating VHDL libraries. ] |
| vhdllib_architecture.3 | | [ vhdllib_architecture ] |
| vhdllib_glitch_handle.3 | | [ vhdllib_glitch_handle ] |
| vhdllib_logic_system.3 | | [ vhdllib_logic_system ] |
| vhdllib_logical_name.3 | | [ vhdllib_logical_name ] |
| vhdllib_pulse_handle.3 | | [ vhdllib_pulse_handle ] |
| vhdllib_tb_compare.3 | | [ vhdllib_tb_compare ] |
| vhdllib_tb_x_eq_dontcare.3 | | [ vhdllib_tb_x_eq_dontcare ] |
| vhdllib_timing_mesg.3 | | [ vhdllib_timing_mesg ] |
| vhdllib_timing_xgen.3 | | [ vhdllib_timing_xgen ] |
| vhdlout_architecture_name.3 | | [ vhdlout_architecture_name ] |
| vhdlout_bit_type.3 | | [ vhdlout_bit_type ] |
| vhdlout_bit_type_resolved.3 | | [ vhdlout_bit_type_resolved ] |
| vhdlout_bit_vector_type.3 | | [ vhdlout_bit_vector_type ] |
| vhdlout_conversion_functions.3 | | [ vhdlout_conversion_functions ] |
| vhdlout_dont_write_types.3 | | [ vhdlout_dont_write_types ] |
| vhdlout_equations.3 | | [ vhdlout_equations ] |
| vhdlout_local_attributes.3 | | [ vhdlout_local_attributes -- NOTE, THIS VARIABLE IS
OBSOLETE. Please use the dc_shell command
'write_script' instead. ] |
| vhdlout_one_name.3 | | [ vhdlout_one_name ] |
| vhdlout_package_naming_style.3 | | [ vhdlout_package_naming_style ] |
| vhdlout_preserve_hierarchical_types.3 | | [ vhdlout_preserve_hierarchical_types ] |
| vhdlout_separate_scan_in.3 | | [ vhdlout_separate_scan_in ] |
| vhdlout_single_bit.3 | | [ vhdlout_single_bit ] |
| vhdlout_target_simulator.3 | | [ vhdlout_target_simulator ] |
| vhdlout_three_state_name.3 | | [ vhdlout_three_state_name ] |
| vhdlout_three_state_res_func.3 | | [ vhdlout_three_state_res_func ] |
| vhdlout_time_scale.3 | | [ vhdlout_time_scale ] |
| vhdlout_top_configuration_arch_name.3 | | [ vhdlout_top_configuration_arch_name ] |
| vhdlout_top_configuration_entity_name.3 | | [ vhdlout_top_configuration_entity_name ] |
| vhdlout_top_configuration_name.3 | | [ vhdlout_top_configuration_name ] |
| vhdlout_unknown_name.3 | | [ vhdlout_unknown_name ] |
| vhdlout_upcase.3 | | [ vhdlout_upcase ] |
| vhdlout_use_packages.3 | | [ vhdlout_use_packages ] |
| vhdlout_wired_and_res_func.3 | | [ vhdlout_wired_and_res_func ] |
| vhdlout_wired_or_res_func.3 | | [ vhdlout_wired_or_res_func ] |
| vhdlout_write_architecture.3 | | [ vhdlout_write_architecture ] |
| vhdlout_write_attributes.3 | | [ vhdlout_write_attributes -- NOTE, THIS VARIABLE IS
OBSOLETE. Please use the dc_shell command
'write_script' instead. ] |
| vhdlout_write_components.3 | | [ vhdlout_write_components ] |
| vhdlout_write_constraints.3 | | [ vhdlout_write_constraints -- NOTE, THIS VARIABLE IS
OBSOLETE. Please use the dc_shell command
'write_script' instead. ] |
| vhdlout_write_entity.3 | | [ vhdlout_write_entity ] |
| vhdlout_write_top_configuration.3 | | [ vhdlout_write_top_configuration ] |
| vhdlout_zero_name.3 | | [ vhdlout_zero_name ] |
| view_analyze_file_suffix.3 | | [ view_analyze_file_suffix ] |
| view_arch_types.3 | | [ view_arch_types ] |
| view_background.3 | | [ view_background ] |
| view_cache_images.3 | | [ view_cache_images ] |
| view_command_log_file.3 | | [ view_command_log_file ] |
| view_command_win_max_lines.3 | | [ view_command_win_max_lines. ] |
| view_dialogs_modal.3 | | [ view_dialogs_modal ] |
| view_disable_cursor_warping.3 | | [ view_disable_cursor_warping ] |
| view_disable_error_windows.3 | | [ view_disable_error_windows ] |
| view_disable_output.3 | | [ view_disable_output ] |
| view_error_window_count.3 | | [ view_error_window_count ] |
| view_execute_script_suffix.3 | | [ view_execute_script_suffix ] |
| view_log_file.3 | | [ view_log_file ] |
| view_on_line_doc_cmd.3 | | [ view_on_line_doc_cmd ] |
| view_read_file_suffix.3 | | [ view_read_file_suffix ] |
| view_script_submenu_items.3 | | [ view_script_submenu_items ] |
| view_set_selecting_color.3 | | [ view_set_selecting_color ] |
| view_tools_menu_items.3 | | [ view_tools_menu_items ] |
| view_use_small_cursor.3 | | [ view_use_small_cursor ] |
| view_use_x_routines.3 | | [ view_use_x_routines ] |
| view_variables.3 | | [ view_variables List of variables that affect the Design
Analyzer viewer. ] |
| view_write_file_suffix.3 | | [ view_write_file_suffix ] |
| which.2 | | [ which Displays the pathname of one or more
files. ] |
| while.2 | | [ while Loop execution control structure. ] |
| write.2 | | [ write Writes a design netlist or schematic
from dc_shell to a file. ] |
| write_cell_transition.3 | | [ write_cell_transition ] |
| write_clusters.2 | | [ write_clusters Writes to a file the physical cluster
annotations associated with a design. ] |
| write_constraints.2 | | [ write_constraints
Writes constraints for the Place and
Route layout tools to a disk file. ] |
| write_design_lib_paths.2 | | [ write_design_lib_paths
Writes the paths to which design
libraries are mapped to a file (in
.synopsys_vss.setup or
.synopsys_dc.setup format). ] |
| write_lib.2 | | [ write_lib Writes a compiled library to disk in
Synopsys database, EDIF, or VHDL format. ] |
| write_name_nets_same_as_ports.3 | | [ write_name_nets_same_as_ports ] |
| write_net_transition.3 | | [ write_net_transition ] |
| write_script.2 | | [ write_script Writes dc_shell commands to save the
current settings. ] |
| write_test.2 | | [ write_test Formats the test patterns for the
current_design into one or more test
vector files. ] |
| write_test_formats.3 | | [ write_test_formats ] |
| write_test_include_scan_cell_info.3 | | [ write_test_include_scan_cell_info ] |
| write_test_input_dont_care_value.3 | | [ write_test_input_dont_care_value ] |
| write_test_max_cycles.3 | | [ write_test_max_cycles ] |
| write_test_max_scan_patterns.3 | | [ write_test_max_scan_patterns ] |
| write_test_pattern_set_naming_style.3 | | [ write_test_pattern_set_naming_style ] |
| write_test_protocol.2 | | [ write_test_protocol
Writes a test protocol file. ] |
| write_test_scan_check_file_naming_style.3 | | [ write_test_scan_check_file_naming_style ] |
| write_test_variables.3 | | [ write_test_variables
Variables that affect the write_test
command. ] |
| write_test_vector_file_naming_style.3 | | [ write_test_vector_file_naming_style ] |
| write_timing.2 | | [ write_timing Writes leaf cell pin-to-pin timing
information to a disk file. ] |
| x11_display_string.3 | | [ x11_display_string ] |
| x11_is_color.3 | | [ x11_is_color ] |
| x11_set_cursor_background.3 | | [ x11_set_cursor_background ] |
| x11_set_cursor_foreground.3 | | [ x11_set_cursor_foreground ] |
| x11_set_cursor_number.3 | | [ x11_set_cursor_number ] |
| x11_vendor_release_number.3 | | [ x11_vendor_release_number ] |
| x11_vendor_string.3 | | [ x11_vendor_string ] |
| x11_vendor_version_number.3 | | [ x11_vendor_version_number ] |
| xnfin_dff_clock_enable_pin_name.3 | | [ xnfin_dff_clock_enable_pin_name ] |
| xnfin_dff_clock_pin_name.3 | | [ xnfin_dff_clock_pin_name ] |
| xnfin_dff_data_pin_name.3 | | [ xnfin_dff_data_pin_name ] |
| xnfin_dff_q_pin_name.3 | | [ xnfin_dff_q_pin_name ] |
| xnfin_dff_reset_pin_name.3 | | [ xnfin_dff_reset_pin_name ] |
| xnfin_dff_set_pin_name.3 | | [ xnfin_dff_set_pin_name ] |
| xnfin_family.3 | | [ xnfin_family ] |
| xnfin_ignore_pins.3 | | [ xnfin_ignore_pins ] |
| xnfout_clock_attribute_style.3 | | [ xnfout_clock_attribute_style ] |
| xnfout_constraints_per_endpoint.3 | | [ xnfout_constraints_per_endpoint ] |
| xnfout_default_time_constraints.3 | | [ xnfout_default_time_constraints ] |
| xnfout_library_version.3 | | [ xnfout_library_version ] |