Command Reference 2. Synopsys Commands create_test_clock
NAME
create_test_clock
Defines the timing of a clock applied to
a design during manufacturing test.
SYNTAX
int create_test_clock ports -waveform edge_list [-
period period_value]
list ports
list edge_list
float period_value
ARGUMENTS
ports List of clock ports with the specified
timing.
-waveform edge_list
Specifies the rise and fall edge times
of the clock over one period. The first
time in the list is always interpreted
as a rising transition, typically the
first rising transition after time zero.
The second time is interpreted as a
falling transition. The list must
contain two values.
-period period_value
Specifies the period of the clock.
Typically, period_value is the same for
all the test clocks of a design. If not
specified, the period_value associated
with the test protocol for the design is
used. If no test protocol has been
defined for a design, the value of the
environment variable test_default_period
is used.
DESCRIPTION
Defines the timing of a clock applied to one or more
input ports of the design during manufacturing test.
Typically, these values are a function of the
performance of the design and the properties of the
automatic test equipment used.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-1
create_test_clock 2. Synopsys Commands Command Reference
The values specified by create_test_clock influence
scan test design rule checking by check_test and
formatting of automatically generated test patterns
into test program files by write_test. The test
program and simulation files output by write_test use
the defined clock timing.
create_test_clock creates three attributes on each of
the listed input ports: test_clock_period,
test_clock_rise_time, and test_clock_fall_time.
report_test -port lists the values of these attributes,
if present, for all ports of the design.
To undo the effect of create_test_clock, use
reset_design or remove_attribute.
If check_test is run without the timing of test clocks
previously defined, default timing waveforms are
inferred for each test clock port. This inferencing
process includes setting the appropriate attributes
values for the clock ports in question.
As an alternative to create_test_clock, the timing of
test clocks can be defined in a test protocol file and
read in using read_test_protocol. In addition, the
timing of any test clocks is included in the test
protocol files created by write_test_protocol.
Note: create_test_clock has no impact on timing
reports, constraint evaluation, or logic optimization.
EXAMPLES
This example defines the test clock timing for the port
"PHI1" with period of 100.0, rise at 50.0, fall at
59.5.
dc_shell> create_test_clock> "PHI1"
-period 100.0 -waveform {50.0 59.5}
In the following example, the test clock has a falling
edge at 35.0, and a rising edge at 45.0, with a period
of 100.0. The falling edge time could also be
specified as 135.0, the next falling edge after the
first rise edge at 45.0. In this case, the value will
automatically be adjusted to 35.0 before setting the
attribute values.
2-2 Synopsys Inc. 1988-1994. All rights reserved. V3.1
Command Reference 2. Synopsys Commands create_test_clock
dc_shell create_test_clock> "PHI2"
-period 100.0 -waveform {45.0 35.0}
This example defines the test clock timing for the port
"PHI3", rise at 300.0, fall at 450.0. A default value
will be used for the period.
dc_shell create_test_clock "PHI3"
-waveform {300.0 450.0}
SEE ALSO
check_test(2), read_test_protocol(2), report_test(2),
write_test(2), write_test_protocol(2);
system_variables: current_design(3),
test_default_period(3).
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-3