set_test_isolate 2. Synopsys Commands Command Reference
NAME
set_test_isolate
Specifies that cells, pins or ports are
logically isolated and considered
untestable during test design rule
checking.
SYNTAX
int set_test_isolate object_list
list object_list
ARGUMENTS
object_list Lists the sequential leaf cells, pins
and ports in the current_design to be
isolated. If more than one object is
specified, they must be enclosed in
braces ({}).
DESCRIPTION
Assigns the test_isolate attribute to object_list. This
indicates to the test design rule checker that the
identified circuitry is untestable and isolated from
its environment. For the purpose of test pattern
generation, if the driver of a net is isolated, then
the net is considered uncontrollable: its value will
remain unknown. This command should be used with
caution since it suppresses the warning messages
associated with the isolated components.
Judisciously used, set_test_isolate can control how
scan test rule checking handles different types of rule
violations. For example, one can use set_test_isolate
to identify cells and pins where rule violations are
known to occur in order to reduce the amount of
messages produced. Isolating a sequential cell will
make it into a black box without any further checks.
Applying set_test_isolate to an otherwise valid cell
will reduce the fault coverage achieved by test pattern
generation.
Another typical use of set_test_isolate is to control
the place where a combinational feedback loop is
broken. When test design rule checking encounters a
combinational feedback loop in a design, it makes an
arbitrary decision on where to break that loop for the
purposes of test pattern generation. The pin where the
loop is broken is automatically isolated by injecting a
logic unknown value at that pin in the test pattern
2-412 Synopsys Inc. 1988-1994. All rights reserved. V3.1
Command Reference 2. Synopsys Commands set_test_isolate
generation network. set_test_isolate can be used to
force a particular pin in a combinational feedback loop
to be the one isolated. In some cases, this can give
better fault coverage results than if the default pin
is used.
A third possible application is to use set_test_isolate
on ports of the design in order to force the test
generation algorithm not to use them. This strategy can
be used to force the vectors through the TDI and TDO
ports of a JTAG design, if all the parallel ports are
isolated.
Isolating a non-sequential cell is an error, since the
only effect of this is to artificially reduce the fault
coverage.
Use report_test -assertions to list the test_isolate
attributes on a design.
To remove selected or all test_isolate attributes from
a design, use remove_attribute. reset_design removes
all attributes from a design, including test_isolate.
V3.1 Synopsys Inc. 1988-1994. All rights reserved. 2-413
set_test_isolate 2. Synopsys Commands Command Reference
EXAMPLES
The following example specifies that the pin MYRSFLOP/R
is to be isolated:
dc_shell> set_test_isolate MYRSFLOP/R
The following example specifies that the cells U3/U1
and U3/U2 are to be isolated:
dc_shell> set_test_isolate {U3/U1,U3_U2}
SEE ALSO
check_test(2), current_design(2), remove_attribute(2),
report_test(2), reset_design(2).
2-414 Synopsys Inc. 1988-1994. All rights reserved. V3.1