Command Reference 2. Synopsys Commands create_wire_load
NAME
create_wire_load
Creates wire load model(s) for the
current design.
SYNTAX
int create_wire_load [-design design_name] [-name model_name] [-cluster cluster_name]
[-output file_name] [-hierarchy] [-trim trim_value] [-percentile percentile_value]
[-statistics] [-dont_smooth]
string design_name
string model_name
string cluster_name
string file_name
float trim_value
float percentile_value
ARGUMENTS
-design design_name
Specifies the design name to create wire
load models for. The default is to
create wire load models for the current
design.
-name model_name
This is the name of the wire load model
to create. This option is incompatible
with the hierarchy option where multiple
wire load models are created. By
default the wire load model name is
created by appending "_wl" to the design
name or the cluster name.
-cluster cluster_name
Specifies a cluster to create a wire
load model for. If the hierarchy option
is used, wire load models are created
for the specified cluster and its sub-
clusters. Without the hierarchy option,
all nets in the cluster and its sub-
clusters are used to create one wire
load model. The cluster name can be
hierarchical (using /) to specify a
lower level cluster.
-output file_name
Specifies the name of the file where the
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create_wire_load 2. Synopsys Commands Command Reference
created wire load models are stored.
With this option, the models created are
not set on the design.
-hierarchy Specifies that wire load models should
be created for the design and each of
its sub-designs. If the design has
clusters (physical grouping
information), this option specifies to
create a wire load model for each
cluster.
-trim trim_value
Specifies the percentage of annotated
nets not taken into account for
calculating the average value.
trim_value is a number between 0 and 50
but must be less than 50. The default is
10, where the 10% lowest annotated
capacitances and 10% of the highest
annotated capacitances are not used in
the average calculation. The trim value
allows you to avoid using the lowest and
highest annotated values, thus
increasing the accuracy of the model
created. No trim will be done for
fanouts with less than 10 annotated
capacitances.
-percentile percentile_value
Specifies how the "average" value is
calculated. By default the percentile
value is 0 and the value chosen for the
fanout is the average of all annotated
capacitances. Specify percentile_value
with a number between 0 and 100. The
percentile_value is the percentage of
nets with an annotated capacitance below
the capacitance value chosen for a
fanout. For example with 100
capacitances annotated for a fanout, and
a percentile_value of 85, the
capacitance value chosen for the fanout
is the 85th highest annotated
capacitance. This option allows to add
pessimism using a percentile_value
greater than 50 or add optimism using a
percentile_value smaller than 50.
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Command Reference 2. Synopsys Commands create_wire_load
-statistics Specifies to report statistics for the
models created. The statistics report
shows for each fanout the ranges from
minimum to maximum capacitance values
annotated and with an 'X' the value
chosen for the fanout. A second graph
shows how many nets (in absolute and
percentage) are below the value chosen
(they have a negative delta capacitance
range) and how many nets are above the
value chosen (they have a positive delta
capacitance range).
-dont_smooth This option specifies not to alter the
averages. By default smoothing is done,
and averages are modified to create a
more realistic model. The smoothing
operations will move the average points
such that the load never decreases when
fanout increases. Linear approximation
is used to make the model's curve
regularly increasing while giving a
higher weight to averages calculated
from a high number of data. Pessimism
is also introduced for high fanout nets.
Use dont_smooth option to avoid
modifying the averages.
DESCRIPTION
Creates wire load models from the capacitances
annotated on nets in the design. If the design has no
net capacitance annotated, no wire load model is
created. Use hierarchy option to create a wire load
model for each level of the design hierarchy. Use the
hierarchy option with cluster information on the design
to create a wire load model for each cluster in the
design. Without the hierarchy option, only one model is
created, using annotated nets in the design and its
sub-designs. Use the cluster option to create a wire
load for a cluster. Use the output option to store the
created models in a text file. With the output option,
the wire load models created are not set on the design.
The wire load models can be updated from the text file
into a library already loaded in memory with
update_lib. update_lib will reset the wire load model
of the current design if that wire load model is
modified.
Use the options trim and percentile to increase the
accuracy and pessimism of the model created. Use the
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create_wire_load 2. Synopsys Commands Command Reference
statistics option to get statistics on the model's
accuracy. By default, create_wire_load modifies the
averages calculated to create a realistic model and
increase pessimism for high fanout nets. Use the
dont_smooth option to avoid modifying the averages. Do
not use the dont_smooth option if you want to create a
realistic model.
Use report_wire_load to report on wire load models on
the design. Use set_wire_load to set and remove wire
load models on designs and clusters. Note, if the
option hierarchy was used, each design in the hierarchy
was set with a wire load model. reset_design and
set_wire_load reset the wire load model on the current
design only.
This command requires both 'DC-Expert' and 'Floorplan-
Management' licenses.
EXAMPLES
The following example creates and sets a wire load
model on the current design. Annotated nets at the top
level and in sub-designs are used. The wire load model
mode for the current design is set to 'top'.
dc_shell> create_wire_load
In the next example, one wire load model is created and
set on each level of the hierarchy with annotated net
capacitances. The wire load model mode is set to
'enclosed' for the current design. If the current
design has clusters annotated, a model is created for
each cluster, if the design has no cluster annotated, a
model is created for each design in the hierarchy of
the current design.
dc_shell> create_wire_load -hierarchy
In the following example, a wire load model is created
and stored in the technology file 'my_lib.lib'. The
model created is NOT set on the current design. The
model is then saved in the 'asic_lib' library.
dc_shell> create_wire_load -output my_lib.lib
dc_shell> update_lib -overwrite asic_lib my_lib.lib
In the following example, a wire load model is created
for cluster 'cl1/cl2' and all of its sub-clusters.
Cluster 'cl1/cl2' is a cluster of cluster 'cl1'. The
wire load models created are set on each cluster in the
cluster hierarchy under 'cl1/cl2'.
dc_shell> create_wire_load -cluster cl1/cl2 -hierarchy
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Command Reference 2. Synopsys Commands create_wire_load
SEE ALSO
current_design(2), read_clusters(2),
report_clusters(2), set_wire_load(2), update_lib(2),
report_wire_load(2).
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