Command Reference 2. Synopsys Commands write_test
NAME
write_test Formats the test patterns for the
current_design into one or more test
vector files.
SYNTAX
int write_test [-format test_program_format] [-output
file] [-input vector_file]
[-first n_patterns] [-revision revision] [-part_number part_number]
string test_program_format
string file
string vector_file
int n_patterns
string revision
string part_number
ARGUMENTS
-format test_program_format
Selects the format for the output test
program. test_program_format must be a
format as defined by the
write_test_formats variable.
-output file Specifies the path and base filename for
the test program files. By default, test
program files are written in the current
directory, using the current design name
as the base filename.
-input vector_file
Specifies the database file containing
the patterns generated by the
create_test_patterns command. The
default filename is design_name.vdb.
write_test uses the system variable
search_path to find the directory
containing this file.
-first n_patterns
Specifies to create test program files
consisting only of the first n patterns
for the design. By default, all
patterns are used in constructing the
test program files. This option is
useful if only a subset of the test
program is required, for example, to run
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write_test 2. Synopsys Commands Command Reference
a representative simulation of the scan
test sequence to check for any timing
problems.
-revision revision
Specifies a design revision string to be
documented in the test program.
-part_number part_number
Specifies a part number string to be
documented in the test program.
-parallel Specifies to generate parallel loadable
test program. This argument is supported
for Verilog and VHDL formats only.
DESCRIPTION
Assembles the scan-test patterns generated for the
current_design by create_test_patterns, into a series
of test program files suitable for running on automatic
test equipment (ATE) or simulators. The current_design
must contain scan-test circuitry either created with
insert_test or manually generated. In both cases, the
check_test command must also have been run to extract
details of the scan-chains within the design, and to
verify the scan-test protocol used.
The output test program is intended as input to
manufacturing automatic test equipment. The program
specifies the stimuli to be applied to a fabricated
chip, and the responses that a fully working chip
generates. If during the testing process, the chip does
not generate the correct responses when the stimuli are
applied, the chip is faulty and should be discarded.
write_test reorganizes the generated test patterns to
reflect the order and polarity of the scan cells in the
design's scan-path. Two types of test program file are
created: one contains the formatted scan test patterns
for the design's functional logic, and the other
contains vectors to specifically test the scan-path
circuitry. The names used for these two types of file
are controlled by the environment variables
write_test_vector_file_naming_style, and
write_test_scan_check_file_naming_style.
The organization of the test program, in terms of the
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Command Reference 2. Synopsys Commands write_test
precise scan-test sequence employed, is determined by
the scan-test protocol for the design. Typically a
simple default protocol inferred by the check_test
command is used. However, it is also possible to
defined a custom protocol for a design, by creating a
test protocol text file which can be read the the
read_test_protocol command. For example, for a
boundary scan design it may be necessary to use the
JTAG TAP protocol as part of the scan-test sequence.
By default the values used for the four timing options
are those specified in the test protocol file for the
design. If a default protocol has been used (inferred
by the check_test command), then the default timing
values will be controlled by the environment variables:
test_default_period, test_default_strobe,
test_default_delay, test_default_bidir_delay. In
addition, the timing of any clock signals can again be
specified in a test protocol file, or directly using
the create_test_clock command.
By default, all test vectors are placed into a single
test program file. Some automatic test equipment
imposes limitations on the size of a single test set.
For these cases, the user can use the
write_test_max_cycles and/or
write_test_max_scan_patterns to control the maximum
number of tester cycles and/or the maximum number of
scan patterns, respectively, contained in a single test
program file. Some ASIC vendors do have specific limits
for these values, e.g. 160,000 vectors and 750
patterns. If multiple test program files are created,
each file will be self-contained. That is, the vectors
within a specific file are independent of the state of
the device under test, and specifically do not require
the vectors in other files to have been previously
applied. This implies test sets can only be
partitioned for full scan designs but not partial scan
designs. Additionally, the partitioning of the vector
set has no effect on fault coverage.
The values accepted by the -format option are
controlled by the environment variable
write_test_formats. This variable is used to list the
formats you wish to make available within your
environment. Note that the choice of available formats
is also controlled by whether or not the Custom Test
Vector Interface option to the Test Compiler product
has been purchased. By default the formats available
are: Verilog, VHDL, TSSI TDS and WGL formats and
-Synopsys. Purchase of the Custom Test Vector Interface
makes available a series of ASIC vendor specific
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write_test 2. Synopsys Commands Command Reference
formats and additional simulator formats. For more
information on the supported test program formats,
refer to the Test Compiler Reference Manual.
During the process of creating test vector files, Test
Compiler creates a temporary intermediate data
structure called SIF (Synopsys Intermediate Format),
which stores all the data required to generate the
target format. This structure is processed to generate
the final vector output file(s). Depending on the
required output format, some or all of the SIF format
data is processed. Some output formats can be
generated into different syntaxes. For instances, some
vector formats support reporting of information
specific to each scan cell (for example, its name and
inversion polarity) in order to permit parallel
simulation of the scan data. An environmental
variable, write_test_include_scan_cell_info, governs
whether this information will be created in those
formats that can optionally support it.
EXAMPLES
The following command writes out a test program for the
design "HUNSLEY", using the default format (Synopsys):
dc_shell> current_design = HUNSLEY
dc_shell> write_test
Assembling test program file HUNSLEY_schk.vec...
Assembling test program file HUNSLEY_schk.sdf...
Assembling test program file HUNSLEY_0.vec...
Assembling test program file HUNSLEY_0.sdf...
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Two pairs of files are created. The files with the
_schk component are the vectors which test the scan-
path circuitry. The other files contain the actual
formatted scan test patterns. One type of file is the
signal definition file (.sdf suffix), which lists
design ports in order. The other type of file (.vec
suffix) contains the actual test vectors.
The following commands create a test program for a
design using the Verilog format and demonstrates how a
test program may be partitioned across multiple files
by specification of a maximum of 100 scan patterns
within a single test program file via the
write_test_max_scan_patterns variable. Additionally,
the base output file name has been specified to be
"PARTITION", and revision and part-number documentation
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Command Reference 2. Synopsys Commands write_test
values have been specified:
dc_shell> write_test_max_scan_patterns = 100
dc_shell> write_test -format verilog -o PARTITION
-part_number "A123" - revision "1.01a"
Assembling test program file PARTITION_0.v...
Assembling test program file PARTITION_1.v...
Assembling test program file PARTITION_2.v...
Assembling test program file PARTITION_schk.v...
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Two set of files are created. One is the test program
to test the scan chain (_schk.v file). The other files
contain the actual test vectors which have been
partitioned across 3 different files: PARTITION_0.v,
PARTITION_1.v, and PARTITION_2.v.
Finally, the following command writes out a parallel
loadable test program for the design "HUNSLEY" using
the Verilog format, into files which names start with
the word para :
dc_shell> current_design = HUNSLEY
dc_shell> write_test -format verilog -parallel -output para
Assembling test program file para_0.v...
Assembling test program file para_schk.v...
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SEE ALSO
check_test(2), create_test_clock(2),
create_test_patterns(2), current_design(2),
insert_test(2), read_test_protocol(2); search_path(3),
test_default_bidir_delay(3), test_default_delay(3),
test_default_period(3), test_default_strobe(3),
verilogout_single_bit(3), vhdlout_single_bit(3),
write_test_formats(3),
write_test_include_scan_cell_info(3).
write_test_max_cycles(3),
write_test_max_scan_patterns(3).
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