Command Reference    2.  Synopsys Commands             trace_nets



NAME
          trace_nets     Enables global net tracing during
                         check_test on the specified nets in the
                         current_design.


SYNTAX
          int trace_nets hierarchical_net_list

          list hierarchical_net_list


ARGUMENTS
          hierarchical_net_list
                         A set of hierarchical net names for
                         which tracing should be enabled.  The
                         net names are separated by commas.  If a
                         net name specified in the
                         hierarchical_net_list is comprised of a
                         partial net name and one or more
                         asterisks (*), the asterisks are used as
                         prefix values for a wildcard net search.
                         That is, all nets containing the
                         associated partial net name specified
                         will be processed by the command.


DESCRIPTION
          Using the check_test command, Test Compiler design rule
          checking (DRC) is performed by doing a symbolic
          simulation of the test protocol for a design.

          If the data applied at the scan in ports is
          successfully and predictably loaded into the scan
          chain, the cells are scan controllable.  If data can be
          captured into the scan cells during the parallel
          capture cycle, and successfully and predictably
          unloaded, the cells are scan observable.  When
          sequential cells are neither fully scannable (both scan
          controllable and scan observable) nor valid nonscan
          cells (for partial scan designs), fault coverage
          suffers.

          Test Compiler provides a net tracing capability that
          allows you to view the results of the symbolic
          simulation to help in the identification and correction
          of test protocol problems.  Test Compiler displays the
          logic values of the nets as information messages.  All
          output from the design rule checker, including
          information messages, is linked to the design
          schematic.  You can debug your protocol by selecting
          nets with certain values, then viewing the



V3.1      Synopsys Inc. 1988-1994. All rights reserved.       2-1

trace_nets           2.  Synopsys Commands      Command Reference



          corresponding section in the schematic through the
          Design Analyzer.

          Net tracing is enabled in either of two fashions. If
          trace_nets statements are added to vector or stream
          groups within a custom test protocol supplied by the
          designer, they enable tracing within a local scope
          limited to that vector or stream group.  Alternatively,
          by specifying nets using the trace_nets command, nets
          can be traced within the global scope of the entire
          current test protocol.  The untrace_nets command acts
          only on nets specified by the trace_nets command.


EXAMPLES
          To enable tracing on all the nets in
          a_given_level_of_hierarchy, execute


                         dc_shell> trace_nets {a_given_level_of_hierarchy*}


          To enable tracing on all the nets containing the name
          fragment `foo', execute


                         dc_shell> trace_nets {*foo*}


SEE ALSO
          check_test(2), system_variables(3), current_design(3).
























2-2       Synopsys Inc. 1988-1994. All rights reserved.      V3.1