set_minimize_tree_delay 2.  Synopsys Commands         Command Reference



NAME
          set_minimize_tree_delay
                         Determines whether an arithmetic
                         expression tree will be restructured to
                         minimize delay during compile.  By
                         default, all expression trees are
                         candidates for tree height minimization
                         if timing constraints are specified.


SYNTAX
          int set_minimize_tree_delay [flag] [-design
          design_list]

          Boolean flag
          list design_list


ARGUMENTS
          flag           Determines the value to which the
                         minimize_tree_delay attribute is to be
                         set.  Values are true (the default) or
                         false.


          -design design_list
                         An optional argument that specifies a
                         list of designs on which to set the
                         minimize_tree_delay attribute.  If not
                         specified, current_design is assumed.


DESCRIPTION
          Determines whether expression trees (for example, adder
          chains) are restructured to minimize delay during
          compile.  The restructuring of arithmetic expression
          trees is based on the arrival times of inputs to the
          tree.  In the case of equal arrival times, a balanced
          tree is constructed.  By default, if timing constraints
          are specified, all arithmetic expression trees are
          restructured to minimize delay, unless otherwise
          specified.

          For more details on tree height minimization, refer to
          the VHDL Compiler Reference manual or the Verilog
          Compiler Reference manual.

          To remove the minimize_tree_delay attribute, use
          remove_attribute.  Alternatively, you can set
          minimize_tree_delay to false, which has the same effect
          as removing it.  reset_design removes all attributes
          from a design, including map_only.



2-368     Synopsys Inc. 1988-1994. All rights reserved.      V3.1

Command Reference       2.  Synopsys Commands   set_minimize_tree_delay



EXAMPLES
          In this example, minimize_tree_delay is enabled on the
          design TEST.


                         dc_shell> set_minimize_tree_delay -design TEST


          In this example, minimize_tree_delay is enabled on the
          current_design.  minimize_tree_delay is disabled on the
          design OLD.


                         dc_shell> read TEST

                         dc_shell> set_minimize_tree_delay

                         dc_shell> set_minimize_tree_delay false -design OLD


SEE ALSO
          current_design(2), compile(2), remove_attribute(2),
          reset_design(2), attributes(3).
































V3.1      Synopsys Inc. 1988-1994. All rights reserved.     2-369