NAME

ioexnxl.diag − Test that Lance data transfers can generate various exceptions. 

DESCRIPTION

Various parity errors and bus errors are caused during a DMA transfer between the memory and the lance circuit. 

DETAILS

Because a Data Parity Error (in this case instituted by using the Memory board’s PECTL register) causes problems on the bus, this test is loaded resident to the instruction cache.  Since running from in the instruction cache prevents any bus accesses for the instructions, data parity errors can be forced without making it impossible for the CPU to correctly interpret its next instruction sequence. 

BOARDS THAT MUST BE INSTALLED

This test requires a CPU board, at least one memory board, an I/O board, and a SCSI adaptor board to be installed in the I/O board. 

COMMAND LINE PARAMETERS

None

MENU ITEMS SPECIFIC TO THIS TEST

sePerform various kinds of I/O exceptions using the SCSI channels. 

INTERPRETING THE ERROR CODES

The following errors may be generated by this test.  (The actual error wording may differ, however the type of error is as summarized here.) 

(un-numbered)
This error message reports that a forced data parity error for a specified numbered byte did not occur.  The possible reports show errors as: "DPE(Byte_4) on" through "DPE(Byte_7 on".

101This message indicates that an attempt to force a Boot Error failed. 

103The test tried to generate an RPE error (requester parity).  The error did not occur. 

105The test tried to force a DPE error (data parity) but the exception did not occur. 

107An unexpected exception occured.  The type of exception is reported. 

501A DMA, once started, has completed too quickly. 

503A DMA timeout has happened. 

505I/O initiator test has tried to find a memory board to use for data transfer and no memory board has responded. 

September 02, 1992