MAKE(1) SysV MAKE(1)
NAME
make - update and regenerate programs or groups of programs
SYNOPSIS
make [-f makefile] [-p] [-i] [-k] [-s] [-r] [-n] [-b] [-e] [-t] [-q]
[names]
DESCRIPTION
make allows the programmer to update and regenerate programs and groups
of programs through the use of assembled rules and dependencies present
in the specified makefile.
make executes commands in makefile to update one or more target names.
Name is typically a program. If no -f option is present, makefile,
Makefile, and the Source Code Control System (SCCS) files, s.makefile and
s.Makefile, are tried in order. If you use a dash (-) in place of
makefile, the standard input is taken. More than one - makefile argument
pair may appear.
make updates a target when its dependents have been more recently created
or modified. All prerequisite files of a target are added recursively to
the list of targets. Missing files are considered to be out-of-date.
Makefile contains a sequence of entries that specify dependencies. The
first line of an entry is a blank-separated, non-null list of targets,
followed by a colon (:), and then a (possibly null) list of prerequisite
files or dependencies. If a name appears on the left of more than one
single-colon line, it is dependent on all the names to the right of the
colon on those lines, though only one command sequence may be specified.
If a name appears on a line with a double colon (::), the command
sequence following that line is performed if the name is out of date with
the names to the right of the double colon. This command sequence is not
affected by other double colon lines on which that name may appear. Text
following a semicolon (;), as well as all following lines beginning with
a tab, are shell commands to be executed in updating the target. The
first non-empty line beginning with a character other than tab or pound
sign (#) will begin a new dependency or macro definition. Shell commands
may be continued across lines with a <backslash><newline> sequence.
Everything printed by make (except the initial tab) is passed directly to
the shell as it is present in the makefile. For these reasons,
echo a\
b
produces
ab
in the same manner as would occur in the shell.
The pound sign (#) and newline surround comments.
The following makefile establishes a dependency where pgm depends on two
files a.o and b.o, and they in turn depend on their corresponding source
files (a.c and b.c) as well as a common file incl.h:
pgm: a.o b.o
cc a.o b.o -o pgm
a.o: incl.h a.c
cc -c a.c
b.o: incl.h b.c
cc -c b.c
Command lines are executed one at a time, each by its own shell. In the
makefile, the make macro SHELL can be used to set the shell for
execution. The default shell for execution is /bin/sh. The following
special characters may be used to begin a shell command singly, or in
combination, to specify the appropriate behavior(s).
A line is printed when it is executed unless the -s option is present, or
the entry .SILENT: is in makefile, or unless the initial character
sequence contains a @. The -n option specifies printing without
execution; however, if the shell command line contains the string $(MAKE)
or the initial character sequence contains the + special character, the
line is always executed (see discussion of the MAKEFLAGS macro under
Environment). The -t (touch) option updates the modified date of a file
without executing any commands.
Commands returning non-zero status normally terminate make. If the -i
option is present, or the entry .IGNORE: appears in makefile, or the
initial character sequence of the command contains -, the error is
ignored. If the -k option is present, work is abandoned on the current
entry, but continues on other branches that do not depend on that entry.
The -b option allows old makefiles (those written for the old version of
make) to run without errors.
Interrupt and quit cause the target to be deleted unless the target is a
dependent of the special name .PRECIOUS.
OPTIONS
-f makefile Description file name. makefile is assumed to be the name
of a description file. A filename of - denotes the standard
input. If there are no -f arguments, the file named
makefile or Makefile or s.[mM]akefile in the current
directory is read. The contents of the description files
override the built-in rules if they are present.
-p Prints out the complete set of macro definitions and target
descriptions.
-i Ignores error codes returned by invoked commands. This mode
is entered if the fake target name .IGNORE appears in the
description file.
-k Abandons work on the current entry if it fails, but
continues on other branches that do not depend on that
entry.
-s Silent mode. Does not print command lines before executing.
This mode is also entered if the fake target name .SILENT
appears in the description file.
-r Does not use the built-in rules.
-n No execute mode. Prints commands, but does not execute
them. Even lines beginning with an @ are printed.
-b Compatibility mode for old makefiles.
-e Environment variables override assignments within makefiles.
-t Touches the target files (causing them to be up-to-date)
rather than issue the usual commands.
-q Question. The make command returns a zero or non-zero
status code depending on whether the target file is or is
not up-to-date.
-d Prints make internal debugging information.
SPECIAL NAMES
.DEFAULT If a file must be made but there are no explicit commands or
relevant built-in rules, the commands associated with the
name .DEFAULT are used if it exists.
.PRECIOUS Dependents of this target will not be removed when quit or
interrupt are hit.
.SILENT Same effect as the -s option.
.IGNORE Same effect as the -i option.
ENVIRONMENT
make reads the environment, assuming all variables to be macro
definitions and processing them appropriately. The environment variables
are processed before any makefile and after the internal rules. As a
result of this, macro assignments in a makefile override environment
variables. The -e option causes the environment to override the macro
assignments in a makefile. Suffixes and their associated rules in the
makefile will override any identical suffixes in the built-in rules.
The MAKEFLAGS environment variable is processed by make as containing any
legal input option (except -f and -p) defined for the command line. Upon
invocation, make "invents" the variable if it is not in the environment,
puts the current options into it, and passes it on to invocations of
commands. MAKEFLAGS always contains the current input options, without
the leading -. This proves very useful for "super-makes." In fact, as
noted above, when the -n option is used, the command $(MAKE) is executed
anyway; hence, one can perform a make -n recursively on a whole software
system to see what would have been executed. This is because the -n is
put in MAKEFLAGS and passed to further invocations of $(MAKE). This is
one way of debugging all of the makefiles for a software project without
actually doing anything.
make also supports the MFLAGS macro. This is for compatability with BSD
environments.
INCLUDE FILES
If the string include appears as the first seven letters of a line in a
makefile, and is followed by a blank or a tab, the rest of the line is
assumed to be a file name and will be read by the current invocation,
after substituting for any macros.
MACROS
Entries of the form string1 = string2 are macro definitions. String2 is
defined as all characters up to a comment character or an unescaped
newline. Subsequent appearances of $(string1[:subst1=[subst2]]) are
replaced by string2. The parentheses are optional if a single character
macro name is used and there is no substitute sequence. The optional
:subst1=subst2 is a substitute sequence. If it is specified, all non-
overlapping occurrences of subst1 in the named macro are replaced by
subst2. Strings (for the purposes of this type of substitution) are
delimited by blanks, tabs, newline characters, and beginnings of lines.
An example of the use of the substitute sequence is shown under
Libraries.
INTERNAL MACROS
There are five internally maintained macros which are useful for writing
rules for building targets.
$* The macro $* stands for the file name part of the current dependent
with the suffix deleted. It is evaluated only for inference rules.
$@ The $@ macro stands for the full target name of the current target.
It is evaluated only for explicitly named dependencies.
$< The $< macro is only evaluated for inference rules or the .DEFAULT
rule. It is the module which is out-of-date with respect to the
target (i.e., the ``manufactured'' dependent file name). Thus, in
the .c.o rule, the $< macro would evaluate to the .c file. An
example for making optimized .o files from .c files is:
.c.o:
cc -c -O $*.c
or:
.c.o:
cc -c -O $<
$? The $? macro is evaluated when explicit rules from the makefile are
evaluated. It is the list of prerequisites that are out-of-date
with respect to the target; essentially, those modules which must be
rebuilt.
$% The $% macro is only evaluated when the target is an archive library
member of the form lib(file.o). In this case, $@ evaluates to lib
and $% evaluates to the library member, file.o.
Four of the five macros can have alternative forms. When an upper-case D
or F is appended to any of the four macros, the meaning is changed to
``directory part'' for D and ``file part'' for F. Thus, $(@D) refers to
the directory part of the string $@. If there is no directory part, ./
is generated. The only macro excluded from this alternative form is $?.
VPATH is another special macro. The VPATH macro is a a list of
directories separated by colons. When make searches for a file as a
result of a dependent relation, it first searches the current directory,
followed by each of the directories on the VPATH list. If it finds the
file, it uses the actual path to the file, as opposed to just the
filename. If VPATH is not defined, make searches only the current
directory.
VPATH is useful when compiling several programs from the same source.
The source may be contained in one directory while each set of object
files, with a separate makefile, may reside in individual subdirectories.
The VPATH macro would point to the source directory in this case.
SCCSDIR is another special macro. The SCCSDIR macro, when specified as
SCCS, allows make to find s. files in the sub-directory SCCS. Otherwise,
make will only find s. files in the current directory.
SUFFIXES
Certain names (for instance, those ending with .o) have inferable
prerequisites such as .c, .s, etc. If no update commands for such a file
appear in makefile, and if an inferable prerequisite exists, that
prerequisite is compiled to make the target. In this case, make has
inference rules that allow files to be built from other files by
examining the suffixes and determining an appropriate inference rule to
use.
A tilde in the rules refers to an SCCS file. See sccsfile(4) for more
information about these files. Thus, the rule .c~.o transforms an SCCS C
source file into an object file (.o). Because the s. of the SCCS files
is a prefix, it is incompatible with make's suffix point of view. Hence,
the tilde is a way of changing any file reference into an SCCS file
reference.
make infers prerequisites for files for which makefile gives no
construction commands. Prerequisites are inferred according to selected
suffixes listed as the prerequisites for the special name .SUFFIXES.
Multiple lists accumulate, while an empty list clears the information
that came before. Order is significant. The first possible name for
existent files and rules is inferred as described in the next paragraph.
The default list is defined in /usr/lib/make/standard.
A rule with only one suffix (i.e., .c:) is the definition of how to build
x from x.c. In effect, the other suffix is null. This is useful for
building targets from only one source file (e.g., shell procedures,
simple C programs).
The -p option for printing the internal rules will display the list of
suffixes implemented on the current machine. Multiple suffix lists
accumulate; .SUFFIXES: with no dependencies clears the list of suffixes.
INFERENCE RULES
The first example can be done more briefly.
pgm: a.o b.o
cc a.o b.o -o pgm
a.o b.o: incl.h
This is because make has a set of internal rules for building files. The
user may add rules to this list by simply putting them in the makefile.
Certain macros are used by the default inference rules to permit the
inclusion of optional matter in any resulting commands. For example,
CFLAGS, LFLAGS, and YFLAGS are used for compiler options to cc(1),
lex(1), and yacc(1), respectively. Again, the previous method for
examining the current rules is recommended.
The inference of prerequisites can be controlled. The rule to create a
file with suffix .o from a file with suffix .c is specified as an entry
with .c.o: as the target and no dependents. Shell commands associated
with the target define the rule for making a .o file from a .c file. Any
target that has no slashes in it and starts with a dot is identified as a
rule and not a true target.
LIBRARIES
If a target or dependency name contains parentheses, it is assumed to be
an archive library, the string within parentheses referring to a member
within the library. Thus lib(file.o) and $(LIB)(file.o) both refer to an
archive library which contains file.o. (This assumes the LIB macro has
been previously defined.) The expression $(LIB)(file1.o file2.o) is not
legal.
Rules pertaining to archive libraries have the form .XX.a where the XX is
the suffix from which the archive member is to be made. An unfortunate
byproduct of the current implementation requires the XX to be different
from the suffix of the archive member. Thus, one cannot have lib(file.o)
depend upon file.o explicitly. The most common use of the archive
interface follows. Here, we assume the source files are all C type
source:
lib: lib(file1.o) lib(file2.o) lib(file3.o)
@echo lib is now up-to-date
.c.a:
$(CC) -c $(CFLAGS) $<
$(AR) $(ARFLAGS) $@ $*.o
rm -f $*.o
In fact, the .c.a rule listed above is built into make and is unnecessary
in this example. A more interesting, but more limited example of an
archive library maintenance construction follows:
lib: lib(file1.o) lib(file2.o) lib(file3.o)
$(CC) -c $(CFLAGS) $(?:.o=.c)
$(AR) $(ARFLAGS) lib $?
rm $?
@echo lib is now up-to-date
.c.a:;
Here the substitution mode of the macro expansions is used. The $? list
is defined to be the set of object file names (inside lib) whose C source
files are out-of-date. The substitution mode translates the .o to .c.
(Unfortunately, one cannot as yet transform to .c~; however, this may
become possible in the future.) Note also, the disabling of the .c.a:
rule, which would have created each object file, one by one. This
particular construct speeds up archive library maintenance considerably.
This type of construct becomes very cumbersome if the archive library
contains a mix of assembly programs and C programs.
NOTES
Some commands return non-zero status inappropriately; use -i to overcome
the difficulty.
BUGS
Filenames with the equal sign (=), colon (:), dollar ($), or at sign (@)
characters will not work. Commands that are directly executed by the
shell, notably cd(1), are ineffectual across newlines in make. The
syntax (lib(file1.o file2.o file3.o) is illegal. You cannot build
lib(file.o) from file.o. The macro $(a:.o=.c~) does not work. Named
pipes are not handled well.
FILES
[Mm]akefile, s.[Mm]akefile, and $(SCCSDIR)/s.[Mm]akefile
/bin/sh
/usr/lib/make/standard
/usr/lib/make/local
SEE ALSO
cc(1), lex(1), yacc(1), printf(3S), cd(1), sh(1).